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1. 发明申请

US20060269054A1 Extending the range of computational fields of intergers 有权
标题翻译：扩展了intergers的计算领域范围
公开(公告)号：US20060269054A1
公开(公告)日：2006-11-30
申请号：US11497496
申请日：2006-08-01
申请人： Itai Dror , Carmi Gressel , Michael Mostovoy , Alexay Molchanov
发明人： Itai Dror , Carmi Gressel , Michael Mostovoy , Alexay Molchanov
IPC分类号： H04L9/28
CPC分类号： G06F7/724 , G06F7/728
摘要： An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
摘要翻译：串行/并行蒙哥马利模拟乘法的扩展，如先前由申请人实现的同时还原，适用于创新地在素数和基于GF（2Q）的多项式的数字字段中执行，以简化操作数的流动的方式，通过执行多预期功能来增强先前的乘法程序。

2. 发明授权

US07904719B2 Extending the range of computational fields of integers 有权
标题翻译：扩展整数的计算领域范围
公开(公告)号：US07904719B2
公开(公告)日：2011-03-08
申请号：US11497496
申请日：2006-07-31
申请人： Itai Dror , Carmi David Gressel , Michael Mostovoy , Alexay Molchanov
发明人： Itai Dror , Carmi David Gressel , Michael Mostovoy , Alexay Molchanov
IPC分类号： G06F7/72 , H04K1/00
CPC分类号： G06F7/724 , G06F7/728
摘要： An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
摘要翻译：串行/并行蒙哥马利模乘法的扩展，如先前由申请人实现的同时减少，适应创新地在素数和基于GF（2q）多项式的数字字段中进行，以简化通过执行多重预期功能来增强以前的乘法程序，操作数的流动。

3. 发明申请

US20120137152A1 REDUCTION OF POWER CONSUMPTION FOR DATA ERROR ANALYSIS 审中-公开
标题翻译：减少数据错误分析的功耗
公开(公告)号：US20120137152A1
公开(公告)日：2012-05-31
申请号：US13313669
申请日：2011-12-07
申请人： Itai Dror , Alexander Berger , Michael Mostovoy , Yoav Weinberg
发明人： Itai Dror , Alexander Berger , Michael Mostovoy , Yoav Weinberg
IPC分类号： G06F1/32 , G06F11/00
CPC分类号： G06F11/1048 , G06F1/3225 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： A controller (e.g., a memory controller) includes initial error analysis logic (e.g., a section of a Reed Solomon or BCH codeword decoder) that determines an error count for a data element. The data element may be data stored in the memory of a memory device (e.g., a flash memory device) that incorporates the controller. Comparison logic in the controller determines when the error count exceeds a power control threshold. When the error count exceeds the power control threshold, control logic in the controller reduces the operational speed of subsequent error analysis logic (e.g., a different section of the Reed Solomon or BCH codeword decoder) for the data element. For example, the subsequent error analysis logic may be error locator logic, such as Chien search logic, that determines where the errors exist in the data element.
摘要翻译：控制器（例如，存储器控制器）包括确定数据元件的错误计数的初始误差分析逻辑（例如，里德所罗门或BCH码字解码器的一部分）。数据元素可以是存储在包含控制器的存储器件（例如，闪存器件）的存储器中的数据。控制器中的比较逻辑确定错误计数何时超过功率控制阈值。当误差计数超过功率控制阈值时，控制器中的控制逻辑降低数据元件的后续误差分析逻辑（例如，里德所罗门或BCH码字解码器的不同部分）的操作速度。例如，后续的错误分析逻辑可以是错误定位器逻辑，诸如Chien搜索逻辑，其确定错误存在于数据元素中的位置。

4. 发明授权

US06748410B1 Apparatus and method for modular multiplication and exponentiation based on montgomery multiplication 有权
标题翻译：基于montgomery乘法的乘法和乘法的装置和方法
公开(公告)号：US06748410B1
公开(公告)日：2004-06-08
申请号：US09480102
申请日：2000-01-10
申请人： Carmi David Gressel , Isaac Hadad , Itai Dror , Alexey Molchanov , Michael Mostovoy
发明人： Carmi David Gressel , Isaac Hadad , Itai Dror , Alexey Molchanov , Michael Mostovoy
IPC分类号： G06F738
CPC分类号： G06F7/728
摘要： This invention discloses apparatus and methods for accelerating processing, loading and unloading of data, from and to a plurality of memory addresses in a CPU having an accumulator, and to a memory-mapped coprocessing device for continuous integer computations.
摘要翻译：本发明公开了一种用于加速处理，加载和卸载数据的装置和方法，该装置和方法来自具有累加器的CPU中的多个存储器地址，以及用于连续整数计算的存储器映射协处理装置。

5. 发明授权

US07111166B2 Extending the range of computational fields of integers 有权
标题翻译：扩展整数的计算领域范围
公开(公告)号：US07111166B2
公开(公告)日：2006-09-19
申请号：US09854853
申请日：2001-05-14
申请人： Itai Dror , Carmi David Gressel , Michael Mostovoy , Alexey Molchanov
发明人： Itai Dror , Carmi David Gressel , Michael Mostovoy , Alexey Molchanov
IPC分类号： G06F7/72 , H04K1/00
CPC分类号： G06F7/724 , G06F7/728
摘要： An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
摘要翻译：串行/并行蒙哥马利模拟乘法的扩展，如先前由申请人实现的同时还原，适用于创新地在素数和基于GF（2Q）的多项式的数字字段中执行，以简化操作数的流动的方式，通过执行多预期功能来增强先前的乘法程序。

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