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1. 发明申请

US20160285704A1 TECHNOLOGIES FOR DYNAMIC NETWORK ANALYSIS AND PROVISIONING 审中-公开
标题翻译：动态网络分析与提供技术
公开(公告)号：US20160285704A1
公开(公告)日：2016-09-29
申请号：US14671326
申请日：2015-03-27
申请人： Iosif Gasparakis , Michael Kounavis
发明人： Iosif Gasparakis , Michael Kounavis
IPC分类号： H04L12/26
CPC分类号： H04L41/142 , H04L43/08
摘要： Technologies for performing network analysis of a network include a network analytics node to determine one or more features of network traffic of the network. Each feature includes indexes associated with a link property, a protocol, and a time property. The network analytics node monitors the network traffic of the network based on the one or more features and generates one or more observation vectors. Each observation vector includes a plurality of the one or more features based on the monitored network traffic. The network analytics node performs a statistical network analysis of the network traffic based on the generated one or more observation vectors to generate a probabilistic model of the network traffic.
摘要翻译：用于执行网络的网络分析的技术包括网络分析节点以确定网络的网络流量的一个或多个特征。每个功能包括与链接属性，协议和时间属性相关联的索引。网络分析节点基于一个或多个特征监视网络的网络流量，并且生成一个或多个观察向量。每个观测向量包括基于所监视的网络业务的多个一个或多个特征。网络分析节点基于所生成的一个或多个观测向量对网络流量进行统计网络分析，以生成网络流量的概率模型。

2. 发明授权

US08533246B2 Carry bucket-aware multiplication having bits with most significant bits set to zero 有权
标题翻译：进位桶识别乘法，其最高有效位的位设置为零
公开(公告)号：US08533246B2
公开(公告)日：2013-09-10
申请号：US12334230
申请日：2008-12-12
申请人： Vinodh Gopal , Michael Kounavis , Arun Raghunath
发明人： Vinodh Gopal , Michael Kounavis , Arun Raghunath
IPC分类号： G06F11/00 , G06F7/52 , G06F5/01 , G06F7/00 , G06F7/44
CPC分类号： G06F7/4991 , G06F7/53 , G06F2207/3832
摘要： An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.
摘要翻译：一种装置，包括被配置为接受多个操作数的集成电路; 将产生结果的操作数乘以第一个二进制格式; 并且以第二二进制格式在多个数据单元中以第一二进制格式分配结果，每个单元具有设置为零的k> 0个最高有效位的W位。

3. 发明授权

US08340280B2 Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations 有权
标题翻译：使用单指令多数据（SIMD）指令来加速伽罗瓦计数器模式（GCM）计算
公开(公告)号：US08340280B2
公开(公告)日：2012-12-25
申请号：US12157961
申请日：2008-06-13
申请人： Shay Gueron , Michael Kounavis
发明人： Shay Gueron , Michael Kounavis
IPC分类号： H04L29/06
CPC分类号： H04L9/0643 , H04L9/0637 , H04L2209/046 , H04L2209/12 , H04L2209/38
摘要： In one embodiment, an encryption operation may be performed by obtaining a product of a carry-less multiplication using multiple single instruction multiple data (SIMD) multiplication instructions each to execute on part of first and second operands responsive to an immediate datum associated with the corresponding instruction, and reducing the product modulo g to form a message authentication code of a block cipher mode. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，可以通过使用多个单指令多数据（SIMD）乘法指令获得无进位乘法的乘积来执行加密操作，每个指令在第一和第二操作数的一部分上响应于与相应的指令，并减少产品模数g以形成分组密码模式的消息认证码。描述和要求保护其他实施例。

4. 发明申请

US20100153830A1 CARRY BUCKET-AWARE MULTIPLICATION 有权
标题翻译：执行BUCKET-AWARE MULTIPLICATION
公开(公告)号：US20100153830A1
公开(公告)日：2010-06-17
申请号：US12334230
申请日：2008-12-12
申请人： Vinodh Gopal , Michael Kounavis , Arun Raghunath
发明人： Vinodh Gopal , Michael Kounavis , Arun Raghunath
IPC分类号： G06F11/00 , G06F7/52 , G06F5/01 , G06F7/00 , G06F7/44
CPC分类号： G06F7/4991 , G06F7/53 , G06F2207/3832
摘要： An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.
摘要翻译：一种装置，包括被配置为接受多个操作数的集成电路; 将产生结果的操作数乘以第一个二进制格式; 并且以第二二进制格式在多个数据单元中以第一二进制格式分配结果，每个单元具有设置为零的k> 0个最高有效位的W位。

5. 发明授权

US07707483B2 Technique for performing cyclic redundancy code error detection 有权
标题翻译：执行循环冗余码错误检测的技术
公开(公告)号：US07707483B2
公开(公告)日：2010-04-27
申请号：US11137964
申请日：2005-05-25
申请人： Michael Kounavis
发明人： Michael Kounavis
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6502
摘要： A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include a technique to perform cyclic redundancy code (CRC) generation.
摘要翻译：执行无进位乘法和位反射操作的技术。更具体地，本发明的实施例包括执行循环冗余码（CRC）生成的技术。

6. 发明授权

US07590930B2 Instructions for performing modulo-2 multiplication and bit reflection 有权
标题翻译：执行模2乘法和位反射的指令
公开(公告)号：US07590930B2
公开(公告)日：2009-09-15
申请号：US11136798
申请日：2005-05-24
申请人： Michael Kounavis
发明人： Michael Kounavis
IPC分类号： H03M13/09
CPC分类号： H03M13/09
摘要： A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include an instruction to perform carry-less multiplication and an instruction to perform a bit reflection operation.
摘要翻译：执行无进位乘法和位反射操作的技术。更具体地，本发明的实施例包括执行无进位乘法的指令和执行位反射操作的指令。

7. 发明申请

US20050083935A1 Method and apparatus for two-stage packet classification using most specific filter matching and transport level sharing 有权
标题翻译：使用最具体的过滤器匹配和传输级别共享的两阶段分组分类的方法和装置
公开(公告)号：US20050083935A1
公开(公告)日：2005-04-21
申请号：US10690301
申请日：2003-10-20
申请人： Michael Kounavis , Alok Kumar , Raj Yavatkar , Harrick Vin
发明人： Michael Kounavis , Alok Kumar , Raj Yavatkar , Harrick Vin
IPC分类号： H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , H04L45/00 , H04L47/14 , H04L47/20 , H04L47/2441 , H04L63/0263
摘要： A method and apparatus for two-stage packet classification, the two-stage packet classification scheme including a first stage and a second stage. In the first classification stage, a packet is classified on the basis of the packet's network path. In the second stage of classification, the packet is classified on the basis of one or more transport (or other) fields of the packet. Also disclosed are embodiments of most specific filter matching and transport level sharing, and either one or both of these techniques may be implemented in the two-stage classification method.
摘要翻译：一种用于两阶段分组分类的方法和装置，所述两阶段分组方案包括第一阶段和第二阶段。在第一分类阶段，基于分组的网络路径对分组进行分类。在分类的第二阶段，基于分组的一个或多个传输（或其他）字段对分组进行分类。还公开了最具体的滤波器匹配和传输级别共享的实施例，并且这些技术中的一个或两个可以在两级分类方法中实现。

8. 发明申请

US20190156183A1 DEFENDING NEURAL NETWORKS BY RANDOMIZING MODEL WEIGHTS 审中-公开
公开(公告)号：US20190156183A1
公开(公告)日：2019-05-23
申请号：US16233700
申请日：2018-12-27
申请人： David M. Durham , Michael Kounavis , Oleg Pogorelik , Alex Nayshtut , Omer Ben-Shalom , Antonios Papadimitriou
发明人： David M. Durham , Michael Kounavis , Oleg Pogorelik , Alex Nayshtut , Omer Ben-Shalom , Antonios Papadimitriou
IPC分类号： G06N3/04 , G06N3/063 , G06N3/08 , G06F17/18 , G06F7/58
摘要： The present disclosure is directed to systems and methods for the selective introduction of low-level pseudo-random noise into at least a portion of the weights used in a neural network model to increase the robustness of the neural network and provide a stochastic transformation defense against perturbation type attacks. Random number generation circuitry provides a plurality of pseudo-random values. Combiner circuitry combines the pseudo-random values with a defined number of least significant bits/digits in at least some of the weights used to provide a neural network model implemented by neural network circuitry. In some instances, selection circuitry selects pseudo-random values for combination with the network weights based on a defined pseudo-random value probability distribution.

9. 发明授权

US07646779B2 Hierarchical packet scheduler using hole-filling and multiple packet buffering 失效
标题翻译：分层数据包调度程序使用填充和多个数据包缓冲
公开(公告)号：US07646779B2
公开(公告)日：2010-01-12
申请号：US11020942
申请日：2004-12-23
申请人： Alok Kumar , Michael Kounavis , Raj Yavatkar
发明人： Alok Kumar , Michael Kounavis , Raj Yavatkar
IPC分类号： H04L12/56
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/564
摘要： A hierarchical packet scheduler using hole-filling and multiple packet buffering. Packet references are enqueued into a hierarchical packet scheduler, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers being served by one or more threads, wherein the number of threads serving a particular level is not dependent on the number of schedulers on the particular level. Packet references are dequeued from the hierarchical packet scheduler at a root level scheduler of the one or more schedulers.
摘要翻译：分层分组调度器，使用填充空穴和多个分组缓冲。分组参考被排入到分级分组调度器中，其中分级分组调度器包括一个或多个级别，每个级别包括由一个或多个线程服务的一个或多个调度器，其中服务于特定级别的线程数量不依赖于特定级别的调度程序数量。分组引用在一个或多个调度器的根级调度器处从分层分组调度器出发。

10. 发明授权

US07525962B2 Reducing memory access bandwidth consumption in a hierarchical packet scheduler 失效
标题翻译：降低分层数据包调度程序中的存储器访问带宽消耗
公开(公告)号：US07525962B2
公开(公告)日：2009-04-28
申请号：US11024318
申请日：2004-12-27
申请人： Michael Kounavis , Alok Kumar , Raj Yavatkar
发明人： Michael Kounavis , Alok Kumar , Raj Yavatkar
IPC分类号： H04L12/28
CPC分类号： H04L47/60 , H04L47/50
摘要： Reducing memory access bandwidth consumption in a hierarchical packet scheduler. A hierarchical packet scheduler is maintained, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers, wherein one or more threads serve each level. Scheduling operations are performed at each scheduler of the hierarchical packet scheduler by reading a portion of scheduler state from external memory.
摘要翻译：降低分层数据包调度程序中的存储器访问带宽消耗。维护分级分组调度器，其中分层分组调度器包括一个或多个级别，每个级别包括一个或多个调度器，其中一个或多个线程服务于每个级别。通过从外部存储器读取调度器状态的一部分，在分级分组调度器的每个调度器处执行调度操作。

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