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1. 发明授权

EP0932187B1 Trench etching using borosilicate glass mask 有权
标题翻译：由硼硅玻璃掩模的手段沟槽蚀刻
公开(公告)号：EP0932187B1
公开(公告)日：2005-05-11
申请号：EP98309900.3
申请日：1998-12-03
申请人： International Business Machines Corporation , Infineon Technologies AG , KABUSHIKI KAISHA TOSHIBA
发明人： Ilg, Matthias , Kleinhenz, Richard L. , Nadahara, Soichi , Nunez, Ronald W. , Penner, Klaus , Roithner, Klaus , Srinivasan, Radhika , Sugimoto, Shigeki
IPC分类号： H01L21/308
CPC分类号： H01L21/3081

2. 发明授权

EP0903769B1 Spatially uniform gas supply and pump configuration for large wafer diameters 有权
标题翻译：空间均匀的气体供给装置和泵组件，用于大直径晶片
公开(公告)号：EP0903769B1
公开(公告)日：2004-11-24
申请号：EP98307568.0
申请日：1998-09-17
申请人： Infineon Technologies AG , International Business Machines Corporation
发明人： Muller, Karl P. , Flietner, Bertrand , Roithner, Klaus
IPC分类号： H01J37/32 , C23C16/44
CPC分类号： H01J37/32834 , H01J37/3244

3. 发明公开

EP0932187A3 Trench etching using borosilicate glass mask 有权
标题翻译：由硼硅玻璃掩模的手段沟槽蚀刻
公开(公告)号：EP0932187A3
公开(公告)日：2003-02-26
申请号：EP98309900.3
申请日：1998-12-03
申请人： International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT , KABUSHIKI KAISHA TOSHIBA
发明人： Ilg, Matthias , Kleinhenz, Richard L. , Nadahara, Soichi , Nunez, Ronald W. , Penner, Klaus , Roithner, Klaus , Srinivasan, Radhika , Sugimoto, Shigeki
IPC分类号： H01L21/308
CPC分类号： H01L21/3081
摘要： An improved method for forming semiconductor substrates using BSG avoids the problems associated with conventional TEOS hard mask techniques. The methods comprises providing a semiconductor substrate 1 and applying a conformal layer of borosilicate glass (BSG) 40 on the substrate. A photoresist layer 60 is then formed over the BSG layer and pattern to expose a desired portion of a layer underlying the photoresist layer. Anisotropical etching is then performed through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers 10, 20 are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers 50 may be applied over the BSG layer between the BSG layer and the photoresist layer. The method is especially useful for forming deep trenches in silicon substrates with pad dielectric layers.

4. 发明公开

EP0932187A2 Trench etching using borosilicate glass mask 有权
标题翻译： Grabenätzen手套Borosilikatglas-Maske
公开(公告)号：EP0932187A2
公开(公告)日：1999-07-28
申请号：EP98309900.3
申请日：1998-12-03
申请人： International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT , KABUSHIKI KAISHA TOSHIBA
发明人： Ilg, Matthias , Kleinhenz, Richard L. , Nadahara, Soichi , Nunez, Ronald W. , Penner, Klaus , Roithner, Klaus , Srinivasan, Radhika , Sugimoto, Shigeki
IPC分类号： H01L21/308
CPC分类号： H01L21/3081
摘要： An improved method for forming semiconductor substrates using BSG avoids the problems associated with conventional TEOS hard mask techniques. The methods comprises providing a semiconductor substrate 1 and applying a conformal layer of borosilicate glass (BSG) 40 on the substrate. A photoresist layer 60 is then formed over the BSG layer and pattern to expose a desired portion of a layer underlying the photoresist layer. Anisotropical etching is then performed through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers 10, 20 are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers 50 may be applied over the BSG layer between the BSG layer and the photoresist layer. The method is especially useful for forming deep trenches in silicon substrates with pad dielectric layers.
摘要翻译：使用BSG形成半导体衬底的改进方法避免了与常规TEOS硬掩模技术相关的问题。所述方法包括提供半导体衬底1并在衬底上施加硼硅酸盐玻璃（BSG）40的共形层。然后在BSG层和图案上形成光致抗蚀剂层60以暴露光致抗蚀剂层下面的层的期望部分。然后通过底层的暴露部分，通过位于光致抗蚀剂层和半导体衬底之间的任何其它层，并进入半导体衬底，从而在半导体衬底中形成沟槽，进行非热蚀刻蚀刻。优选地，在施加BSG层之前，在衬底表面上存在一个或多个电介质层10,20。可以在BSG层和光致抗蚀剂层之间的BSG层上施加一个或多个化学屏障和/或有机抗反射涂层50。该方法对于在具有焊盘介电层的硅衬底中形成深沟槽特别有用。

5. 发明公开

EP0844314A2 Distribution plate for a reaction chamber 失效
标题翻译： Verteilerplattefüreine Reaktionskammer
公开(公告)号：EP0844314A2
公开(公告)日：1998-05-27
申请号：EP97309500.3
申请日：1997-11-25
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Roithner, Klaus , Poschenrieder, Bernhard , Muller, Karl Paul
IPC分类号： C23C16/44 , C23F4/00 , H01L21/00
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45561
摘要： The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.
摘要翻译：本发明是一种用于在反应室内安装反应物气体的装置。该装置能够用于气相沉积和蚀刻工艺中。该装置基本上补偿由气体耗尽引起的晶片边缘处的气相沉积和蚀刻不均匀的问题。具有延伸穿过其中的多个孔的气体分配板附接到反应室的内表面。至少一个真空密封隔板设置在气体分配板的表面和室的内表面之间。隔板将板和反应室之间的空间分隔成气体分配区。气体入口连接到每个气体分配区。每个气体入口管线具有至少一个质量流量控制器，其调节到每个气体分配区域的气体流量。质量流量控制器用于确保跨越基板表面的化学气相沉积或蚀刻的均匀速率。

6. 发明公开

EP0844314A3 Distribution plate for a reaction chamber 失效
标题翻译：分配板用于反应室
公开(公告)号：EP0844314A3
公开(公告)日：2001-04-11
申请号：EP97309500.3
申请日：1997-11-25
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Roithner, Klaus , Poschenrieder, Bernhard , Muller, Karl Paul
IPC分类号： C23F4/00 , H01L21/00 , C23C16/455
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45561
摘要： The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.

7. 发明公开

EP1009021A1 Method and assembly for preventing formation of black silicon on edges of wafers 审中-公开
标题翻译：一种用于防止在晶片上的边缘黑硅的形成的方法和组合物
公开(公告)号：EP1009021A1
公开(公告)日：2000-06-14
申请号：EP99309262.6
申请日：1999-11-22
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Perng, Dung-Ching , Wang, Ting Hao , Dobuzinsky, David M. , Roithner, Klaus
IPC分类号： H01L21/308 , H01L21/306 , H01L21/316 , H01L21/8242
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/30604 , H01L21/3081 , H01L21/31612
摘要： A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.
摘要翻译：一种用于通过减少雅舞蹈黑硅沉积本发明的提高芯片的成品率的方法包括：提供适合于制造半导体芯片，用在晶片的整个表面上沉积的第一层，去除所述第一层的一部分的硅晶片的步骤以露出适用于形成半导体器件和蚀刻晶片搜索做的第一层的其余部分阻止蚀刻的材料的再沉积在晶片上的区域。用于在其上的黑硅沉积减少的半导体组件，包括：适合于制造半导体芯片的硅晶片，其具有用于形成半导体器件，一个后表面和边缘的前表面的晶片。的沉积层被形成在晶片上覆盖背面和边缘的搜索没有硅的再沉积的背表面和蚀刻期间晶片的边缘上被阻止。

8. 发明公开

EP0854510A3 Mask removal for etching a DRAM capacitor trench 失效
标题翻译：在DRAM的电容器的沟槽面膜去除
公开(公告)号：EP0854510A3
公开(公告)日：1999-09-08
申请号：EP97310402.9
申请日：1997-12-22
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Muller, Karl Paul , Poschenrieder, Bernhard , Roithner, Klaus
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/31116
摘要： A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.

9. 发明公开

EP0854510A2 Mask removal for etching a DRAM capacitor trench 失效
标题翻译： Entfernung einer Maske beimGrabenätzeneines DRAM-Kondensators
公开(公告)号：EP0854510A2
公开(公告)日：1998-07-22
申请号：EP97310402.9
申请日：1997-12-22
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Muller, Karl Paul , Poschenrieder, Bernhard , Roithner, Klaus
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/31116
摘要： A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.
摘要翻译：使用诸如反应离子蚀刻的各向异性技术来允许去除TEOS蚀刻掩模层的方法。与湿式化学蚀刻技术相比，使用各向异性技术导致焊盘氧化物层的底切显着减少。本发明的一个实施例涉及在焊盘TEOS层下方形成多晶硅蚀刻停止层。

10. 发明授权

EP0844314B1 Recation chamber containing a gas distribution plate 失效
标题翻译：反应室具有内置气体分配板
公开(公告)号：EP0844314B1
公开(公告)日：2004-02-11
申请号：EP97309500.3
申请日：1997-11-25
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Roithner, Klaus , Poschenrieder, Bernhard , Muller, Karl Paul
IPC分类号： C23F4/00 , H01L21/00 , C23C16/455
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45561

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