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1. 发明申请

WO2011084339A2 NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION 审中-公开
标题翻译：具有不同PT组成的镍 - 硅化物形成
公开(公告)号：WO2011084339A2
公开(公告)日：2011-07-14
申请号：PCT/US2010/059607
申请日：2010-12-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FRYE, Asa , SIMON, Andrew
发明人： FRYE, Asa , SIMON, Andrew
IPC分类号： H01L21/336 , H01L29/78 , H01L21/24
CPC分类号： H01L21/28518 , H01L29/665
摘要： Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers (105, 106) over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) (100) through a physical vapor deposition (PVD) process, wherein the first metal layer (105) is deposited using a first nickel target material containing platinum (Pt), and the second metal layer (106) is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel- silicide layer (107) at a top surface of the gate, source, and drain regions.
摘要翻译：本发明的实施例提供了一种形成硅化镍的方法。该方法可以包括通过物理气相沉积（PVD）（PVD）在场效应晶体管（FET）（100）的栅极，源极和漏极区域中的至少一个之上沉积第一和第二金属层（105,106））工艺，其中使用包含铂（Pt）的第一镍靶材料来沉积第一金属层（105），并且使用第二镍靶材料在第一金属层的顶部上沉积第二金属层（106）或者比第一镍靶材中的铂少; 以及对覆盖FET的第一和第二金属层进行退火，以在栅极，源极和漏极区域的顶部表面形成含铂镍硅化物层（107）。

2. 发明申请

WO2004053926A2 A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE 审中-公开
标题翻译：一种在半导体互连结构上沉积金属层的方法
公开(公告)号：WO2004053926A2
公开(公告)日：2004-06-24
申请号：PCT/EP2003/050958
申请日：2003-12-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： MALHOTRA, Sandra , SIMON, Andrew
IPC分类号： H01L
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.
摘要翻译：公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。在该方法中，金属导体被介电层覆盖。图案化电介质层以暴露金属导体。然后将衬垫层沉积到图案中。然后对衬垫层进行氩溅射蚀刻以去除衬里层并暴露金属导体。在氩溅射蚀刻的过程中，衬里层被再沉积到图案的侧壁上。最后，附加层沉积到图案中并覆盖再沉积的衬里层。

3. 发明申请

WO2023021178A1 PHASE CHANGE MEMORY CELL WITH SPACER 审中-公开
公开(公告)号：WO2023021178A1
公开(公告)日：2023-02-23
申请号：PCT/EP2022/073163
申请日：2022-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： OK, Injo , SAULNIER, Nicole , SANKARAPANDIAN, Muthumanickam , SIMON, Andrew , MCDERMOTT, Steven , SARAF, Iqbal
IPC分类号： H01L45/00
摘要： A phase change memory (PCM) cell (100) includes a bottom electrode (104), a heater (108) electrically connected to the bottom electrode, a PCM material (114) electrically connected to the heater, a top electrode (122) electrically connected to the PCM material, an electrical insulator (120) surrounding the PCM material, and a shield (116) positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material, preferably of aluminum nitride, aluminum oxide or aluminum oxynitride.

4. 发明申请

WO2004114395A3 DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS 审中-公开
公开(公告)号：WO2004114395A3
公开(公告)日：2004-12-29
申请号：PCT/EP2004/051046
申请日：2004-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , GAMBINO, Jeffrey , COONEY, Edward, III , STAMPER, Anthony , MOTSIFF, Thomas , LANE, Michael , SIMON, Andrew
发明人： GAMBINO, Jeffrey , COONEY, Edward, III , STAMPER, Anthony , MOTSIFF, Thomas , LANE, Michael , SIMON, Andrew
IPC分类号： H01L21/768
摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

5. 发明申请

WO2004114395A2 DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS 审中-公开
标题翻译：具有不同材料的双线性互连结构用于线路和通道导体
公开(公告)号：WO2004114395A2
公开(公告)日：2004-12-29
申请号：PCT/EP2004/051046
申请日：2004-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , GAMBINO, Jeffrey , COONEY, Edward, III , STAMPER, Anthony , MOTSIFF, Thomas , LANE, Michael , SIMON, Andrew
发明人： GAMBINO, Jeffrey , COONEY, Edward, III , STAMPER, Anthony , MOTSIFF, Thomas , LANE, Michael , SIMON, Andrew
IPC分类号： H01L21/768
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76808 , H01L21/76813 , H01L21/76843 , H01L21/76846 , H01L21/76865 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
摘要翻译：公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

6. 发明申请

WO2004053979A1 A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A CAPPING LAYER 审中-公开
标题翻译：在具有覆盖层的半导体互连结构上沉积金属层的方法
公开(公告)号：WO2004053979A1
公开(公告)日：2004-06-24
申请号：PCT/EP2003/050957
申请日：2003-12-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH , INFINEON TECHNOLOGIES AG
发明人： CLEVENGER, Larry , DALTON, Timothy , HOINKIS, Mark , KALDOR, Steffen , KUMAR, Kaushik , LA TULIPE, Douglas, Jr. , SEO, Soon-Cheon , SIMON, Andrew , WANG, Yun-Yu , YANG, Chih-Chao , YANG, Haining
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
摘要翻译：公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。对电介质层进行图案化以使覆盖层露出。然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

7. 发明公开

EP1570517A1 A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A CAPPING LAYER 有权
标题翻译：用于沉积金属层上的半导体INTERKONNEKTSTRUKTUR具有表面的方法
公开(公告)号：EP1570517A1
公开(公告)日：2005-09-07
申请号：EP03796085.3
申请日：2003-12-08
申请人： International Business Machines Corporation
发明人： CLEVENGER, Larry , DALTON, Timothy , HOINKIS, Mark , KALDOR, Steffen , KUMAR, Kaushik , LA TULIPE, Douglas, Jr. , SEO, Soon-Cheon , SIMON, Andrew , WANG, Yun-Yu , YANG, Chih-Chao , YANG, Haining
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

8. 发明公开

EP1570518A2 A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE 审中-公开
标题翻译：用于沉积金属层上半导体的方法INTERKONNEKTSTRUKTUR
公开(公告)号：EP1570518A2
公开(公告)日：2005-09-07
申请号：EP03799543.8
申请日：2003-12-08
申请人： International Business Machines Corporation
发明人： MALHOTRA, Sandra , SIMON, Andrew
IPC分类号： H01L21/768
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a dielectric layer (18). The dielectric layer is patterned so as to expose the metal conductor. A liner layer (24) is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor (14). In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer (26) is deposited into the pattern and covers the redeposited liner layer.

9. 发明公开

EP4410076A1 PHASE CHANGE MEMORY CELL WITH SIDEWALL PROJECTION LINER 审中-公开
公开(公告)号：EP4410076A1
公开(公告)日：2024-08-07
申请号：EP22793729.9
申请日：2022-09-27
申请人： International Business Machines Corporation
发明人： BREW, Kevin , PHILIP, Timothy , SIMON, Andrew , SHOUDY, Matthew T. , OK, Injo
IPC分类号： H10N70/20
CPC分类号： H10N70/231 , H10N70/8413 , H10N70/826 , H10N70/8828 , H10N70/011 , H10N70/063

10. 发明公开

EP4388835A1 PHASE CHANGE MEMORY CELL WITH SPACER 审中-公开
公开(公告)号：EP4388835A1
公开(公告)日：2024-06-26
申请号：EP22768348.9
申请日：2022-08-19
申请人： International Business Machines Corporation
发明人： OK, Injo , SAULNIER, Nicole , SANKARAPANDIAN, Muthumanickam , SIMON, Andrew , MCDERMOTT, Steven , SARAF, Iqbal
IPC分类号： H10N70/00
CPC分类号： H10N70/801 , H10N70/231 , H10N70/8413 , H10N70/826 , H10N70/8828 , H10N70/063

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