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1. 发明申请

WO2003054938A1 METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SWITCHES ON CMOS COMPATIBLE SUBSTRATES 审中-公开
标题翻译：在CMOS兼容基板上制作微电子开关的方法
公开(公告)号：WO2003054938A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/036088
申请日：2002-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： VOLANT, Richard, P. , BISSON, John, C. , COTE, Donna, R. , DALTON, Timothy, J. , GROVES, Robert, A. , PETRARCA, Kevin, S. , STEIN, Kenneth, J. , SUBBANNA, Seshadri
IPC分类号： H01L21/20
CPC分类号： B81C1/00246 , B81B2201/016 , B81B2201/018 , B81B2203/0127 , B81B2207/07 , B81C1/00611 , B81C2201/0122 , B81C2203/0735 , H01G5/40 , H01H59/0009
摘要： A method of fabricating micro-electromechanical switches (MEMS) using a process starting with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric (150). All, or portions, of the interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, for example, Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam (160) and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the moveable beam (160) that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material.
摘要翻译：一种使用由铜镶嵌互连层开始的工艺来制造微机电开关（MEMS）的方法，由介于电介质（150）中的金属导体制成。当开关处于闭合状态时，互连件的全部或部分凹陷到足以提供电容气隙的程度，以及为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束（160）并且提供用于切换信号穿过的一个或多个路径。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是沉积到形成开关装置的可移动梁（160）之间形成的间隙的所需厚度的另一介电层。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。

2. 发明申请

WO2006039138A1 HOMOGENEOUS COPPER INTERCONNECTS FOR BEOL 审中-公开
标题翻译：用于BEOL的均质铜互连
公开(公告)号：WO2006039138A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/033539
申请日：2005-09-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PETRARCA, Kevin, S. , KRISHNAN, Mahadevaiyer , LOFARO, Michael , RODBELL, Kenneth, P.
发明人： PETRARCA, Kevin, S. , KRISHNAN, Mahadevaiyer , LOFARO, Michael , RODBELL, Kenneth, P.
IPC分类号： H01L21/31
CPC分类号： H01L21/76873 , H01L21/2855 , H01L21/7684 , H01L21/76877
摘要： Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer (440). The impure copper seed layer (440) covers a barrier layer (230), which covers an insulating layer (115) that has an opening. Electroplated copper fills the opening in the insulating layer (115). Through a chemical mechanical polish, the barrier layer (230), the impure copper seed layer (440) derived from an electroplated copper bath, and the electroplated copper are planarized to the insulating layer (115).
摘要翻译：通过包括不纯铜籽晶层（440）的互连，减轻了用于线路半导体器件后端的铜互连边缘的缺陷。不纯铜种子层（440）覆盖覆盖具有开口的绝缘层（115）的阻挡层（230）。电镀铜填充绝缘层（115）中的开口。通过化学机械抛光，阻挡层（230），源自电镀铜浴的不纯铜种子层（440）和电镀铜平坦化到绝缘层（115）。

3. 发明申请

WO2011119308A2 METHOD OF FORMING A MULTI-CHIP STACKED STRUCTURE INCLUDING A THIN INTERPOSER CHIP HAVING A FACE-TO-BACK BONDING WITH ANOTHER CHIP 审中-公开
标题翻译：形成多芯片堆叠结构的方法，包括具有与另一芯片的面对背结合的薄互连芯片
公开(公告)号：WO2011119308A2
公开(公告)日：2011-09-29
申请号：PCT/US2011/026957
申请日：2011-03-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FAROOQ, Mukta, G. , PETRARCA, Kevin, S. , VOLANT, Richard, P.
发明人： FAROOQ, Mukta, G. , PETRARCA, Kevin, S. , VOLANT, Richard, P.
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L21/6835 , H01L23/3128 , H01L25/50 , H01L2221/68327 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01322 , H01L2924/1305 , H01L2924/00
摘要： A temporary substrate (901) having an array of first solder pads (192) is bonded to the front side of a first substrate (101) by reflowing an array of first solder balls (250). The first substrate (101) is thinned by removing the back side, and an array of second solder pads (142) is formed on the back side surface of the first substrate (101). The assembly of the first substrate (101) and the temporary substrate (901) is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip (100) and a handle portion (900). A second semiconductor chip (200) is bonded to an assembly through an array of the second solder balls (150). The handle portion (900) is removed from each assembly by reflowing the array of the first solder balls (250), while the array of the second solder balls (150) does not refiow. The assembly is subsequently mounted on a packaging substrate (300) employing the array of the first solder balls (250).
摘要翻译：通过回流第一焊球（250）的阵列，将具有第一焊盘（192）阵列的临时衬底（901）结合到第一衬底（101）的正面。通过去除背面来减薄第一衬底（101），并且在第一衬底（101）的后侧表面上形成第二焊盘（142）阵列。切割第一衬底（101）和临时衬底（901）的组件以形成多个堆叠，每个堆叠包括第一半导体芯片（100）和手柄部分（900）的组件。第二半导体芯片（200）通过第二焊球（150）的阵列结合到组件。通过回流第一焊球（250）的阵列而从每个组件移除手柄部分（900），同时第二焊球（150）的阵列不再回流。随后将该组件安装在采用第一焊球（250）的阵列的封装衬底（300）上。

4. 发明申请

WO2011090912A2 INTEGRATED VOID FILL FOR THROUGH SILICON VIA 审中-公开
标题翻译：通过硅的集成无孔填充
公开(公告)号：WO2011090912A2
公开(公告)日：2011-07-28
申请号：PCT/US2011/021446
申请日：2011-01-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , VOLANT, Richard, P. , FAROOQ, Mukta, G. , PETRARCA, Kevin, S.
发明人： VOLANT, Richard, P. , FAROOQ, Mukta, G. , PETRARCA, Kevin, S.
IPC分类号： H01L23/12 , H01L21/60 , H01L23/48
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly and method of forming a through hole extending through a first and second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the wafers. A hole can be etched through the first wafer until a gap is exposed between the confronting faces. The hole can have a first wall and a second wall sloping inwardly from the first wall to an opening through which the gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered creating a wall between the confronting faces. The hole can be etched so as to extend the first wall through the first wafer, such that the wall of the hole extends continuously from the first wafer into the second wafer. An electrically conductive through silicon via can then be formed.
摘要翻译：提供了形成延伸穿过第一和第二晶片的通孔的微电子组件和方法。第一和第二晶片在表面处具有面对面和金属特征，所述表面和金属结合在一起以组装晶片。可以通过第一晶片蚀刻孔，直到在相对面之间露出间隙。孔可以具有从第一壁向内倾斜到间隙露出的开口的第一壁和第二壁。然后可以溅射在孔内露出的第一或第二晶片的材料，从而在相对面之间产生壁。可以蚀刻该孔以使第一壁延伸穿过第一晶片，使得孔的壁从第一晶片连续延伸到第二晶片。然后可以形成导电的硅通孔。

5. 发明申请

WO2005041360A1 FLEXIBLE ASSEMBLY OF STACKED CHIPS 审中-公开
标题翻译：柔性组装块
公开(公告)号：WO2005041360A1
公开(公告)日：2005-05-06
申请号：PCT/US2003/030640
申请日：2003-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , VOLANT, Richard, P. , PETRARCA, Kevin, S. , WALKER, George, F.
发明人： VOLANT, Richard, P. , PETRARCA, Kevin, S. , WALKER, George, F.
IPC分类号： H01R12/00
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2221/68372 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/18 , H01L2224/24137 , H01L2224/48091 , H01L2224/48227 , H01L2224/49431 , H01L2224/49433 , H01L2224/73209 , H01L2224/73259 , H01L2224/73267 , H01L2224/82005 , H01L2224/9222 , H01L2225/06524 , H01L2225/06527 , H01L2225/06579 , H01L2225/06589 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.
摘要翻译：描述了由多个折叠的集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片电连接的互连路径，并且至少一个芯片（130）是具有附加到衬底（500），封装或印刷电路板的互连布线。进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

6. 发明申请

WO2011056374A2 COAXIAL THROUGH-SILICON VIA 审中-公开
标题翻译：同轴通硅氧威盛
公开(公告)号：WO2011056374A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/052594
申请日：2010-10-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , VOLANT, Richard, P. , FAROOQ, Mukta, G. , FINDEIS, Paul, F. , PETRARCA, Kevin, S.
发明人： VOLANT, Richard, P. , FAROOQ, Mukta, G. , FINDEIS, Paul, F. , PETRARCA, Kevin, S.
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate 40. The TSV structure is provided with two or more independent electrical conductors 50, 60 insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.
摘要翻译：硅通孔（TSV）结构在硅衬底40内形成独特的同轴或三轴互连.TSV结构设置有两个或更多个独立的电导体50,60，所述两个或更多个独立的电导体50,60彼此绝缘并从衬底。电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴设备进行操作。使用各种绝缘体材料的多个层可以用作绝缘体，其中这些层基于介电性质，填充性质，界面粘合性，CTE匹配等来选择。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。还描述了制造这种TSV结构的方法。

7. 发明申请

WO2007127816A3 METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES 审中-公开
公开(公告)号：WO2007127816A3
公开(公告)日：2007-11-08
申请号：PCT/US2007/067449
申请日：2007-04-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FAROOQ, Mukta, G. , DAUBENSPECK, Timothy, H. , SAUTER, Wolfgang , GAMBINO, Jeffrey, P. , MUZZY, Christopher, D. , PETRARCA, Kevin, S.
发明人： FAROOQ, Mukta, G. , DAUBENSPECK, Timothy, H. , SAUTER, Wolfgang , GAMBINO, Jeffrey, P. , MUZZY, Christopher, D. , PETRARCA, Kevin, S.
IPC分类号： H01L21/44
摘要： A method for forming preferably Pb-lead C4 connections or capture pads 37 with ball limiting metallization on an integrated circuit chip 30 by using a damascene process and preferably Cu metallization 32 in the chip 30 and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad 52 is formed in the top insulating layer 51 and it also serves as the final level of metallization in the chip.

8. 发明申请

WO2005062367A1 I/O SITES FOR PROBE TEST AND WIRE BOND 审中-公开
标题翻译：用于探测测试和线束的I / O站点
公开(公告)号：WO2005062367A1
公开(公告)日：2005-07-07
申请号：PCT/US2003/037162
申请日：2003-11-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PETRARCA, Kevin, S. , CHENG, Tien-Jen , KNICKERBOCKER, Sarah, H. , VOLANT, Richard, P. , WALKER, George, F.
发明人： PETRARCA, Kevin, S. , CHENG, Tien-Jen , KNICKERBOCKER, Sarah, H. , VOLANT, Richard, P. , WALKER, George, F.
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05109 , H01L2224/05147 , H01L2224/05155 , H01L2224/05176 , H01L2224/05556 , H01L2224/05558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85205 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/0105 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/20754 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A method of forming an input-output (I/0) structure is described, wherein a substrate having copper conductive feature (20) exposed at the bottom of a recess (25) in a first dielectric layer (10) is covered by a first conductive barrier (102) that is selectively formed in the recess (25). A second dielectric (105), preferably an organic polymer such as polyimide, is formed over the substrate surface and a second recess (27) is formed in the second dielectric (105) so that at least a portion of the first conductive barrier (102) is exposed. A second conductive barrier (107) is conformally deposited, followed by conformal deposition of a seed layer (109), where both are deposited under a vacuum to ensure adhesion of the seed layer (109) to the second conductive barrier (107). The seed layer (107) is selectively removed external to the recess (27), followed by plating of a nickel-containing metal (113) and then a noble metal (115), which will plate on the remaining portion of the seed layer (107) in the recess (27), but not on the second barrier layer (107). The second barrier layer (107) is removed from the exposed field areas by a low bias power RIE. The invention provides a low-cost method of forming an I/0 structure for both probe test and wire bond without damage to underlying devices and reduced chip real estate.
摘要翻译：描述了形成输入 - 输出（I / O）结构的方法，其中在第一介电层（10）中的凹部（25）的底部露出的具有铜导电特征（20）的基板被第一导电屏障（102），其选择性地形成在所述凹部（25）中。第二电介质（105），优选有机聚合物（例如聚酰亚胺）形成在衬底表面上，并且第二凹陷（27）形成在第二电介质（105）中，使得至少一部分第一导电屏障（102 ）暴露。第二导电屏障（107）被共形沉积，接着是晶种层（109）的共形沉积，其中两者都在真空下沉积以确保籽晶层（109）与第二导电屏障（107）的粘附。种子层（107）被选择性地移除到凹部（27）的外部，然后镀覆含镍金属（113），然后镀覆贵金属（115），其将在种子层的剩余部分 107），但不在第二阻挡层（107）上。通过低偏置功率RIE从曝光的场区域去除第二阻挡层（107）。本发明提供了一种用于形成用于探针测试和线接合的I / O结构的低成本方法，而不损坏下面的器件并减少芯片的不动产。

9. 发明申请

WO2002065540A1 A COMMON BALL-LIMITING METALLURGY FOR I/O SITES 审中-公开
标题翻译：用于I / O站点的通用限制金属
公开(公告)号：WO2002065540A1
公开(公告)日：2002-08-22
申请号：PCT/US2001/049137
申请日：2001-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： WALKER, George, F. , GOLDBLATT, Ronald, D. , GRUBER, Peter, A. , HORTON, Raymond, R. , PETRARCA, Kevin, S. , VOLANT, Richard, P. , CHENG, Tien-Jen
IPC分类号： H01L21/44
CPC分类号： H01L24/48 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/16 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00015 , H01L2924/00012
摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal (26) on the top surface of the pad, while providing a diffusion barrier (22) to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate (20) are reduced by providing a method for selectively depositing metal layers in a feature (21) formed in the substrate (20). Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.
摘要翻译：描述了用于形成适用于引线键合和焊料凸块倒装芯片连接（例如受控崩溃芯片连接（C4））的公共输入 - 输出（I / O）站点的过程。本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易受到结合力的损害。本发明通过在衬垫的顶表面上提供具有贵金属（26）的位置同时提供扩散阻挡层（22）来保持金属互连的高导电性，从而降低了损坏的风险。通过提供在形成在基板（20）中的特征（21）中选择性地沉积金属层的方法来减少在基板（20）内形成I / O部位的工艺步骤。由于本发明的I / O站点可用于引线键合或焊料凸块连接，这为芯片互连选项提供了增加的灵活性，同时也降低了工艺成本。

10. 发明公开

EP1800335A1 HOMOGENEOUS COPPER INTERCONNECTS FOR BEOL 审中-公开
标题翻译：均匀的铜化合物FOR BEOL
公开(公告)号：EP1800335A1
公开(公告)日：2007-06-27
申请号：EP05797431.3
申请日：2005-09-20
申请人： International Business Machines Corporation
发明人： PETRARCA, Kevin, S. , KRISHNAN, Mahadevaiyer , LOFARO, Michael , RODBELL, Kenneth, P.
IPC分类号： H01L21/31 , H01L21/44 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/76873 , H01L21/2855 , H01L21/7684 , H01L21/76877
摘要： Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer (440). The impure copper seed layer (440) covers a barrier layer (230), which covers an insulating layer (115) that has an opening. Electroplated copper fills the opening in the insulating layer (115). Through a chemical mechanical polish, the barrier layer (230), the impure copper seed layer (440) derived from an electroplated copper bath, and the electroplated copper are planarized to the insulating layer (115).

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