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1. 发明公开

US20240204792A1 Stochastic Rounding Switched Capacitor Computation Cores Useful for Efficient Deep Learning Inference 审中-公开
公开(公告)号：US20240204792A1
公开(公告)日：2024-06-20
申请号：US18085094
申请日：2022-12-20
申请人： International Business Machines Corporation
发明人： Chia-Yu CHEN , Ankur Agrawal , Andrea Fasoli , Kyu-hyoun Kim
IPC分类号： H03M1/38
CPC分类号： H03M1/38
摘要： An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.

2. 发明授权

US11669489B2 Sparse systolic array design 有权
公开(公告)号：US11669489B2
公开(公告)日：2023-06-06
申请号：US17490830
申请日：2021-09-30
申请人： International Business Machines Corporation
发明人： Swagath Venkataramani , Sanchari Sen , Vijayalakshmi Srinivasan , Ankur Agrawal , Sunil K Shukla , Bruce Fleischer , Kailash Gopalakrishnan
IPC分类号： G06F15/80 , G06F9/30 , G06F7/50 , G06F7/544 , G06F7/523
CPC分类号： G06F15/8046 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F9/3001 , G06F9/30069
摘要： A systolic array can be configured to skip distributed operands that have zero-values, resulting in improved resource efficiency. A skip module is introduced to receive operands from memory, identify whether they have a zero value or not, and, if they are nonzero, generate an operand vector including an index before sending the operand vector to a processing element.

3. 发明授权

US11455142B2 Ultra-low precision floating-point fused multiply-accumulate unit 有权
公开(公告)号：US11455142B2
公开(公告)日：2022-09-27
申请号：US16432358
申请日：2019-06-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ankur Agrawal , Silvia Mueller , Kailash Gopalakrishnan , Bruce Fleischer , Balaram Sinharoy , Mingu Kang
IPC分类号： G06F7/544
摘要： Embodiments for implementing a fused multiply-multiply-accumulate (“FMMA”) unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.

4. 发明申请

US20200249910A1 HYBRID FLOATING POINT REPRESENTATION FOR DEEP LEARNING ACCELERATION 审中-公开
公开(公告)号：US20200249910A1
公开(公告)日：2020-08-06
申请号：US16269346
申请日：2019-02-06
申请人： International Business Machines Corporation
发明人： NAIGANG WANG , Jungwook Choi , Kailash Gopalakrishnan , Ankur Agrawal , Silvia Melitta Mueller
IPC分类号： G06F7/483 , G06N3/08
摘要： In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.

5. 发明申请

US20200233642A1 ENHANCED LOW PRECISION BINARY FLOATING-POINT FORMATTING 审中-公开
公开(公告)号：US20200233642A1
公开(公告)日：2020-07-23
申请号：US16840847
申请日：2020-04-06
申请人： International Business Machines Corporation
发明人： Silvia Melitta Mueller , Ankur Agrawal , Bruce Fleischer , Kailash Gopalakrishnan , Dongsoo Lee
IPC分类号： G06F7/499
摘要： Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.

6. 发明申请

US20190339938A1 VERY LOW PRECISION FLOATING POINT REPRESENTATION FOR DEEP LEARNING ACCELERATION 审中-公开
公开(公告)号：US20190339938A1
公开(公告)日：2019-11-07
申请号：US15973511
申请日：2018-05-07
申请人： International Business Machines Corporation
发明人： NAIGANG WANG , Kailash Gopalakrishnan , Jungwook Choi , Silvia M. Mueller , Ankur Agrawal , Daniel Brand
IPC分类号： G06F7/483 , G06F7/499 , G06N3/08
摘要： A specialized circuit is configured for floating point computations using numbers represented by a very low precision format (VLP format). The VLP format includes less than sixteen bits and is apportion into a sign bit, exponent bits (e), and mantissa bits (p). The configured specialized circuit is operated to store an approximation of a numeric value in the VLP format, where the approximation is represented as a function of a multiple of a fraction, where the fraction is an inverse of a number of discrete values that can be represented using only the mantissa bits.

7. 发明授权

US08941415B2 Edge selection techniques for correcting clock duty cycle 有权
标题翻译：用于校正时钟占空比的边沿选择技术
公开(公告)号：US08941415B2
公开(公告)日：2015-01-27
申请号：US14151998
申请日：2014-01-10
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Ankur Agrawal
IPC分类号： H03K17/00 , H03K5/156 , H03K3/017
CPC分类号： H03K17/005 , H03K3/017 , H03K5/1565
摘要： Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.
摘要翻译：提供电路和方法用于产生时钟信号和校正时钟信号中的占空比失真。用于产生时钟信号的电路包括多路复用器电路和边沿触发触发器电路。多路复用器电路选择性地输出多个输入时钟信号中的一个。边沿触发触发器检测从多路复用器电路有选择地输出的输入时钟信号的转变边缘，并且响应于该检测，对接收数据信号进行逻辑电平采样，并产生输出时钟信号在边沿触发的触发器的输出端口。多路复用器电路基于边沿触发的触发器的输出端口处的输出时钟信号的逻辑电平，选择性地将多个输入时钟信号中的一个输出到边沿触发的触发器的时钟信号端口，其被输入到多路复用器电路的选择控制端口。

8. 发明申请

US20140140439A1 Power-Scalable Skew Compensation in Source-Synchronous Parallel Interfaces 有权
标题翻译：源同步并行接口中的功率可伸缩偏移补偿
公开(公告)号：US20140140439A1
公开(公告)日：2014-05-22
申请号：US13683508
申请日：2012-11-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ankur Agrawal , Timothy O. Dickcson , Sergey Rylov
IPC分类号： H04L7/00
CPC分类号： H04L25/14 , G06F1/10 , H04L7/0008 , H04L7/0025
摘要： A parallel receiver interface includes a plurality of parallel data receivers, each receiver receiving input data. A clock receiver is configured to receive a forwarded clock. A phase interpolator has an input coupled to the output of the clock receiver and has an output coupled to each of the parallel receivers. Parallel clock delay elements are within each of the parallel data receivers, each clock delay element configured to provide varying amounts of clock phase adjustment. Inputs of a multiplexer circuit within each of the parallel data receivers are coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver. An output of the multiplexer circuit is coupled to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.
摘要翻译：并行接收器接口包括多个并行数据接收器，每个接收器接收输入数据。时钟接收器被配置为接收转发的时钟。相位内插器具有耦合到时钟接收器的输出的输入，并且具有耦合到每个并行接收器的输出。并行时钟延迟元件在每个并行数据接收器内，每个时钟延迟元件配置成提供不同量的时钟相位调整。每个并行数据接收器内的多路复用器电路的输入耦合到相应的并行数据接收器内的每个并行时钟延迟元件的输出。多路复用器电路的输出耦合到相应的并行数据接收器内的数据采样器，多路复用器电路被配置为由逻辑信号控制。

9. 发明申请

US20130208782A1 TIME DOMAIN ANALOG MULTIPLICATION TECHNIQUES FOR ADJUSTING TAP WEIGHTS OF FEED-FORWARD EQUALIZERS 有权
标题翻译：用于调整进给均衡器的TAP权重的时域模拟多路复用技术
公开(公告)号：US20130208782A1
公开(公告)日：2013-08-15
申请号：US13763659
申请日：2013-02-09
申请人： International Business Machines Corporation
发明人： Ankur Agrawal , John F. Bulzacchelli
IPC分类号： H04L27/01
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to a given FFE tap during the integration period to enable the given FFE tap during a portion of the integration period in which the gating control signal overlaps the integration period so as to effectively multiply the data signal input to the given FFE tap with an FFE coefficient value corresponding to a period of overlap between the gating control signal and the integration period.
摘要翻译：提供前馈均衡器（FFE）电路和方法，其实现时域模拟乘法以调整FFE抽头权重。例如，一种方法包括将数据信号输入到电流积分加法电路的FFE抽头，其中数据信号是模拟输入数据信号的时间延迟版本。在电流积分夏季电路的复位期间，将电容充电至预充电电平。在积分积分电路的积分期间，由每个FFE抽头产生输出电流。来自FFE抽头的输出电流在积分期间共同对电容进行充电或放电。在积分周期期间，门控控制信号被施加到给定的FFE抽头，以便在选通控制信号与积分周期重叠的积分周期的一部分期间实现给定的FFE抽头，以便有效地将输入的数据信号乘以给定的 FFE抽头具有对应于门控控制信号和积分周期之间的重叠周期的FFE系数值。

10. 发明授权

US11347517B2 Reduced precision based programmable and SIMD dataflow architecture 有权
公开(公告)号：US11347517B2
公开(公告)日：2022-05-31
申请号：US16447588
申请日：2019-06-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kailash Gopalakrishnan , Sunil Shukla , Jungwook Choi , Silvia Mueller , Bruce Fleischer , Vijayalakshmi Srinivasan , Ankur Agrawal , Jinwook Oh
IPC分类号： G06F9/38 , G06F15/80
摘要： A reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture includes reduced precision execution units with a majority of the execution units operating at reduced precision and a minority of the execution units are capable of operating at higher precision. The execution units operate in parallel within a programmable execution element to share instruction fetch, decode, and issue pipelines and operate on the same instruction in lock-step to minimize instruction-related overhead.

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