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    • 1. 发明公开
    • A Lateral transistor and method of making same
    • Laltaltransistor和Verfahren zum Herstellen desselben。
    • EP0392954A2
    • 1990-10-17
    • EP90480025.7
    • 1990-02-20
    • International Business Machines Corporation
    • Desilets, Brian HenryHsieh, Chang-MingHsu, Louis Lu-Chen
    • H01L21/285H01L21/331H01L29/73
    • H01L29/6625H01L21/763H01L29/41708H01L29/735Y10S148/05
    • A method of fabricating a lateral transistor (110) is provided, including the steps of: providing a body of semiconductor material including a device region (30) of a first conductivity type (N⁺); patterning the surface of the device region to define a first transistor region (44); filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of said first transistor region; removing portions of the insulating material so as to define a pair of trenches (22) generally bounding opposite sides of the first tran­sistor region; filling the pair of trenches with doped conductive material (26) of opposite conductivity type to the first transistor region; and annealing the semiconduc­tor body whereby to form second and third transistor regions (96,98) of opposite conductivity type to the first transistor region (44) in the opposing sides of the first transistor region completing the process to provide con­tact electrodes (102, 104, 106).
    • 提供一种制造横向晶体管(110)的方法,包括以下步骤:提供包括第一导电类型(N +)的器件区域(30)的半导体材料体; 图案化器件区域的表面以限定第一晶体管区域(44); 用绝缘材料将围绕第一晶体管区域的器件区域的图案化部分填充到大体上等于所述第一晶体管区域的表面的高度; 去除所述绝缘材料的部分以便限定通常围绕所述第一晶体管区域的相对侧的一对沟槽(22); 用与所述第一晶体管区相反的导电类型的掺杂导电材料(26)填充所述一对沟槽; 和退火所述半导体体,从而形成与所述第一晶体管区域的相对侧中的所述第一晶体管区域(44)相反导电类型的第二和第三晶体管区域(96,98),从而完成所述工艺以提供接触电极(102,104 ,106)。
    • 6. 发明公开
    • Plasma etching reactor
    • Plasmaätzreaktor。
    • EP0200133A2
    • 1986-11-05
    • EP86105478.1
    • 1986-04-21
    • International Business Machines Corporation
    • Desilets, Brian HenryGunther, Thomas AnthonyHendricks, Charles JosephKeller, John Howard
    • H01J37/32C23F4/00
    • H01J37/32623H01J37/32633
    • A plasma reactor for uniformly etching a large number of semiconductor wafers (32) at a reduced plasma potential includes, in one embodiment, one or several grounded plates (42) spaced apart from each other and mounted intermediate the cathode (20) and the top plate (40) of a reactor chamber (36), the top plate and the chamber walls forming the reactor anode. The topmost grounded plate (42) is spaced apart from the chamber top plate a distance sufficient to allow a plasma to be established between the grounded plate (42) and the top plate, and the distance between the lowest grounded plate (5) and the cathode is large enough not to disturb the field in the proximity of the wafers (32) being etched. At least one plate can be apertured to facilitate etchant gas flow.
    • 在一个实施例中,用于均匀蚀刻大量半导体晶片(32)的等离子体反应器在一个实施例中包括彼此间隔开并安装在阴极(20)和顶部之间的一个或多个接地板(42) 反应器室(36)的板(40),顶板和室壁形成反应器阳极。 最上面的接地板(42)与腔室顶板隔开足以允许在接地板(42)和顶板之间建立等离子体的距离,以及最低接地板(5)和 阴极足够大,不会干扰蚀刻晶片(32)附近的场。 至少一个板可以开孔以便于蚀刻剂气体流动。