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1. 发明授权

US10678724B1 Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator 有权
公开(公告)号：US10678724B1
公开(公告)日：2020-06-09
申请号：US16236423
申请日：2018-12-29
申请人： Intel Corporation
发明人： Kermin ChoFleming , Simon Steely, Jr. , Kent Glossop
IPC分类号： G06F3/00 , G06F13/24 , H04L29/08 , H04L12/933
摘要： Systems, methods, and apparatuses relating to in-network storage for a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a plurality of processing elements; a circuit switched interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the circuit switched interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements; and an in-network storage element of the circuit switched interconnect network comprising a queue coupled to an output queue of a first processing element, and a controller that switches the in-network storage element into a first mode that provides a value stored in the queue of the in-network storage element by the output queue of the first processing element to an input queue of a second processing element when a configuration value is a first value, and into a second mode that bypasses the queue of the in-network storage element and provides a value from the output queue of the first processing element to the input queue of the second processing element when the configuration value is a second value.

2. 发明授权

US10402176B2 Methods and apparatus to compile code to generate data flow code 有权
公开(公告)号：US10402176B2
公开(公告)日：2019-09-03
申请号：US15855964
申请日：2017-12-27
申请人： Intel Corporation
发明人： Kent Glossop , Kermin Fleming , Yongzhi Zhang , Simon Steely, Jr. , Jim Sukha , Uma Srinivasan
IPC分类号： G06F9/44 , G06F8/41
摘要： Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.

3. 发明授权

US09740617B2 Hardware apparatuses and methods to control cache line coherence 有权
公开(公告)号：US09740617B2
公开(公告)日：2017-08-22
申请号：US14581097
申请日：2014-12-23
申请人： Intel Corporation
发明人： Samantika Sury , Simon Steely, Jr. , William Hasenplaugh , Joel Emer , David Webb
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0817
CPC分类号： G06F12/0833 , G06F12/0822 , G06F2212/283 , Y02D10/13
摘要： Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

4. 发明授权

US10817291B2 Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator 有权
公开(公告)号：US10817291B2
公开(公告)日：2020-10-27
申请号：US16370915
申请日：2019-03-30
申请人： Intel Corporation
发明人： Jesus Corbal , Rohan Sharma , Simon Steely, Jr. , Chinmay Ashok , Kent D. Glossop , Dennis Bradford , Paul Caprioli , Louise Huot , Kermin ChoFleming , Barry Tannenbaum
IPC分类号： G06F9/30 , G06F15/82
摘要： Systems, methods, and apparatuses relating to swizzle operations and disable operations in a configurable spatial accelerator (CSA) are described. Certain embodiments herein provide for an encoding system for a specific set of swizzle primitives across a plurality of packed data elements in a CSA. In one embodiment, a CSA includes a plurality of processing elements, a circuit switched interconnect network between the plurality of processing elements, and a configuration register within each processing element to store a configuration value having a first portion that, when set to a first value that indicates a first mode, causes the processing element to pass an input value to operation circuitry of the processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the processing element, and a second portion that causes the processing element to perform an operation indicated by the second portion the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry.

5. 发明授权

US09727482B2 Address range priority mechanism 有权
公开(公告)号：US09727482B2
公开(公告)日：2017-08-08
申请号：US15275630
申请日：2016-09-26
申请人： Intel Corporation
发明人： Simon Steely, Jr. , Samantika S. Sury , William C. Hasenplaugh
IPC分类号： G06F12/08 , G06F12/12 , G06F12/10 , G06F12/0891 , G06F12/126 , G06F12/1009 , G06F12/1045 , G06F12/128 , G06F12/1027
CPC分类号： G06F12/0891 , G06F12/1009 , G06F12/1027 , G06F12/1054 , G06F12/126 , G06F12/128 , G06F2212/621 , G06F2212/65 , G06F2212/683
摘要： Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.

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