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1. 发明授权

US11755099B2 Dynamic core selection for heterogeneous multi-core systems 有权
公开(公告)号：US11755099B2
公开(公告)日：2023-09-12
申请号：US17852066
申请日：2022-06-28
申请人： Intel Corporation
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32 , G06F1/329 , G06F1/3287 , G06F9/38 , G06F9/50 , G06F11/34 , G06F9/445 , G06F9/48
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3466 , G06F11/3409 , G06F11/3452 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/00 , Y02D30/50
摘要： Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

2. 发明申请

US20190332158A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开
公开(公告)号：US20190332158A1
公开(公告)日：2019-10-31
申请号：US16508916
申请日：2019-07-11
申请人： Intel Corporation
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/329 , G06F9/50 , G06F9/48 , G06F11/34 , G06F9/445 , G06F1/3287 , G06F9/38
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

3. 发明授权

US09317297B2 Replay execution of instructions in thread chunks in the chunk order recorded during previous execution 有权
标题翻译：在先前执行过程中记录的块顺序中重新执行线程块中的指令
公开(公告)号：US09317297B2
公开(公告)日：2016-04-19
申请号：US13629131
申请日：2012-09-27
申请人： Intel Corporation
发明人： Justin E. Gottschlich , Klaus Danne , Cristiano L. Pereira , Gilles A. Pokam , Rolf Kassa , Shiliang Hu , Tim Kranich
IPC分类号： G06F9/44 , G06F9/38 , G06F9/455 , G06F11/30 , G06F11/36 , G06F11/34 , G06F9/52
CPC分类号： G06F9/3005 , G06F9/30072 , G06F9/3802 , G06F9/3851 , G06F9/44 , G06F9/455 , G06F9/52 , G06F11/30 , G06F11/3414 , G06F11/3476 , G06F11/36 , G06F11/3664 , G06F11/3688 , G06F2201/815 , G06F2201/825 , G06F2201/865
摘要： Embodiments may provide a method for performing a replay of a previous execution of a program. The method includes generating an order of recorded chunks of instructions across a plurality of recorded threads based, at least in part, on log files generated from the previous execution of the program. The method includes initiating execution of the program, the executing program having a plurality of threads, each thread having a number of chunks of instructions. The method includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk before the instruction is executed. The method includes determining, by a replay module executing on the processor, that the chunk is an active chunk if the chunk is currently in line for execution according to the order of recorded chunks, and responsive to a determination that the chunk is the active chunk, executing the instruction.
摘要翻译：实施例可以提供用于执行程序的先前执行的重放的方法。该方法包括至少部分地基于从先前执行的程序生成的日志文件来生成跨多个记录的线程的所记录的指令块的顺序。该方法包括启动程序的执行，执行程序具有多个线程，每个线程具有多个指令块。该方法包括在执行指令之前由在处理器上执行的虚拟机单元截取块的指令。该方法包括通过在处理器上执行的重放模块来确定，如果该组块当前正在与行记录在一起以便执行，则根据所记录的块的顺序来确定该块是活动块，并且响应于该块是活动块的确定执行指令。

4. 发明授权

US10007549B2 Apparatus and method for a profiler for hardware transactional memory programs 有权
公开(公告)号：US10007549B2
公开(公告)日：2018-06-26
申请号：US14581772
申请日：2014-12-23
申请人： Intel Corporation
发明人： Justin E. Gottschlich , Gilles A. Pokam , Shiliang Hu
IPC分类号： G06F9/44 , G06F12/08 , G06F9/46 , G06F9/445 , G06F12/084 , G06F9/30 , G06F12/0813 , G06F12/0811
CPC分类号： G06F9/467 , G06F9/3004 , G06F9/30087 , G06F9/44563 , G06F11/3632 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code; and a profiler to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code.

5. 发明授权

US09501135B2 Dynamic core selection for heterogeneous multi-core systems 有权
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US09501135B2
公开(公告)日：2016-11-22
申请号：US14169955
申请日：2014-01-31
申请人： INTEL CORPORATION
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32 , G06F9/38 , G06F9/50 , G06F9/445 , G06F9/48 , G06F11/34
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能度量好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

6. 发明授权

US09342303B2 Modified execution using context sensitive auxiliary code 有权
标题翻译：使用上下文相关的辅助代码修改执行
公开(公告)号：US09342303B2
公开(公告)日：2016-05-17
申请号：US13843940
申请日：2013-03-15
申请人： Intel Corporation
发明人： James E. Smith , Denis M. Khartikov , Shiliang Hu , Youfeng Wu
IPC分类号： G06F9/30 , G06F9/45
CPC分类号： G06F9/30 , G06F8/443 , G06F9/30181 , G06F9/328
摘要： A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.
摘要翻译：用于增强处理器中的架构指令执行的系统和方法使用辅助代码来优化基本微代码的执行。可以对构建的指令的执行上下文进行分析以检测潜在的优化，从而产生和存储辅助微代码。当结构化指令被解码为基本微代码以执行时，可以使用检索的辅助代码来增强或修改基本微代码。

7. 发明授权

US09128781B2 Processor with memory race recorder to record thread interleavings in multi-threaded software 有权
标题翻译：具有内存种族记录器的处理器可在多线程软件中记录线程交错
公开(公告)号：US09128781B2
公开(公告)日：2015-09-08
申请号：US13729718
申请日：2012-12-28
申请人： Intel Corporation
发明人： Tim Kranich , Gilles A. Pokam , Justin E. Gottschlich , Klaus Danne , Rolf Kassa , Shiliang Hu , Cristiano L. Pereira
IPC分类号： G06F9/52 , G06F11/36
CPC分类号： G06F9/526 , G06F11/3404 , G06F11/3409 , G06F11/3471 , G06F11/36 , G06F11/3636
摘要： A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.
摘要翻译：处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。块缓冲区是临时存储块，直到块被从处理器传出。

8. 发明授权

US10534424B2 Dynamic core selection for heterogeneous multi-core systems 有权
公开(公告)号：US10534424B2
公开(公告)日：2020-01-14
申请号：US14986676
申请日：2016-01-02
申请人： Intel Corporation
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/329 , G06F1/3287 , G06F9/38 , G06F9/50 , G06F11/34 , G06F9/445 , G06F9/48
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

9. 发明授权

US10474471B2 Methods and systems for performing a replay execution 有权
公开(公告)号：US10474471B2
公开(公告)日：2019-11-12
申请号：US15131425
申请日：2016-04-18
申请人： Intel Corporation
发明人： Justin E. Gottschlich , Klaus Danne , Cristiano L. Pereira , Gilles A. Pokam , Rolf Kassa , Shiliang Hu , Tim Kranich
IPC分类号： G06F9/44 , G06F9/38 , G06F9/455 , G06F11/30 , G06F11/36 , G06F11/34 , G06F9/30 , G06F9/52
摘要： One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.

10. 发明申请

US20170286111A1 Instruction, Circuits, and Logic for Data Capture for Software Monitoring and Debugging 审中-公开
公开(公告)号：US20170286111A1
公开(公告)日：2017-10-05
申请号：US15089179
申请日：2016-04-01
申请人： Intel Corporation
发明人： Cristiano L. Pereira , Gilles A. Pokam , Shiliang Hu , Beeman C. Strong
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F12/0875 , G06F11/3034 , G06F11/3466 , G06F12/0842 , G06F12/0888 , G06F2201/865 , G06F2212/452
摘要： A processor includes a front end including circuitry to receive an instruction to monitor execution of a thread, a decoder including circuitry to decode the instruction, a scheduler including circuitry to schedule the instruction, a retirement unit including circuitry to retire the instruction, and a core. The core includes circuitry to, based on execution of the instruction, monitor execution of the thread, identify an attempted read of an address during execution of the thread, determine whether a value at the address was previously read during monitoring of the execution of the thread, log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread, and omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.

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