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1. 发明申请

US20150220372A1 TECHNIQUES FOR CONTROLLING USE OF LOCKS 审中-公开
标题翻译：控制锁的使用技术
公开(公告)号：US20150220372A1
公开(公告)日：2015-08-06
申请号：US14129935
申请日：2013-07-15
申请人： INTEL CORPORATION
发明人： Khun Ban , Kingsum Chow , Shirish Aundhe , Sandhya Viswanathan
IPC分类号： G06F9/52 , G06F9/44
CPC分类号： G06F9/52 , G06F8/70 , G06F9/30076 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/528
摘要： Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于控制通过同时执行的代码部分来调节对共享资源的访问的锁的使用的技术。用于控制资源锁定的装置包括处理器组件，历史分析器，用于由处理器组件执行以用锁定标记来分析替换第一代码实例的锁定指令的至少一个结果，以允许处理器组件推测性地执行代码的第二实例，以及用于由处理器组件执行的锁定组件，以基于至少一个结果的分析，用于访问资源的代码的第一和第二实例来代替具有锁定标记的锁定指令，以及锁定指令请求对该资源的访问锁定到第一个代码。描述和要求保护其他实施例。

2. 发明授权

US10120731B2 Techniques for controlling use of locks 有权
公开(公告)号：US10120731B2
公开(公告)日：2018-11-06
申请号：US14129935
申请日：2013-07-15
申请人： INTEL CORPORATION
发明人： Khun Ban , Kingsum Chow , Shirish Aundhe , Sandhya Viswanathan
IPC分类号： G06F12/00 , G06F9/52 , G06F9/30 , G06F9/38 , G06F8/70
摘要： Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.

3. 发明申请

US20180095892A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO DETERMINE PAGE GROUP IDENTIFIERS, AND OPTIONALLY PAGE GROUP METADATA, ASSOCIATED WITH LOGICAL MEMORY ADDRESSES 审中-公开
公开(公告)号：US20180095892A1
公开(公告)日：2018-04-05
申请号：US15283355
申请日：2016-10-01
申请人： Intel Corporation
发明人： Hugh Wilkinson , William R. Wheeler , Shirish Aundhe , Sandhya Viswanathan , David A. Koufaty
IPC分类号： G06F12/1027 , G06F12/14 , G06F9/30
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F12/145 , G06F2212/1052 , G06F2212/68
摘要： A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.

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