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1. 发明申请

WO2017099784A1 FLEXIBLE COMPUTING DEVICE THAT INCLUDES A PLURALITY OF DISPLAYS 审中-公开
标题翻译：灵活的计算设备，包括多个显示器
公开(公告)号：WO2017099784A1
公开(公告)日：2017-06-15
申请号：PCT/US2015/065080
申请日：2015-12-10
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , OOI, Kooi Chi , CHEAH, Bok Eng , GOH, Eng Huat
IPC分类号： G06F1/16 , G09F9/30
CPC分类号： G06F1/1652 , G06F1/163
摘要： A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.
摘要翻译：一种柔性电子装置，其包括具有上表面和下表面的柔性基板以及在所述上表面和所述下表面之间延伸的互连; 直接安装到所述柔性基板的上表面的柔性显示器，使得所述柔性显示器电连接到所述柔性基板; 第一密封剂，其安装到所述柔性衬底的上表面，使得所述柔性显示器至少部分地嵌入所述第一密封剂内; 电子部件，所述电子部件安装到所述柔性基板的下表面，使得所述电子部件电连接到所述柔性基板; 第二密封剂，所述第二密封剂安装到所述柔性基板的所述下表面，使得所述电子组件至少部分地嵌入所述第二密封剂内; 包围电子元件和第二密封剂的柔性外壳。

2. 发明申请

WO2018063639A1 INTERCONNECTS FOR WEARABLE DEVICE 审中-公开
标题翻译：互连器件用于可穿戴设备
公开(公告)号：WO2018063639A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/048914
申请日：2017-08-28
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KOH, Boon Ping , OOI, Kooi Chi , KONG, Jackson Chung Peng
IPC分类号： H05K5/00 , G06F1/16 , H01R12/70
摘要： Various embodiments disclosed relate to a wearable electronic device. One embodiment includes of a wearable electronic device includes a first flexible layer. The first flexible layer includes a first surface and a second surface that is substantially parallel to the first surface. A first electrical component and a second electrical component is attached to the second surface. A transmission line connects the first electrical component and the second electrical component. A voltage reference trace connected to a voltage reference source attached to at least one of the first electrical component or the second electrical component. The device further includes a second flexible layer. The second flexible layer includes a third surface that is substantially parallel to the second surface and facing the second surface. The second flexible layer also includes a fourth surface. The device further includes a voltage reference plane attached to the third surface. An interconnection is formed between the voltage reference trace and the voltage reference plane.
摘要翻译：所公开的各种实施例涉及可穿戴电子设备。一个实施例包括可穿戴电子设备，其包括第一柔性层。第一柔性层包括第一表面和基本平行于第一表面的第二表面。第一电部件和第二电部件附接到第二表面。传输线连接第一电气部件和第二电气部件。连接到电压参考源的电压参考迹线连接到第一电气部件或第二电气部件中的至少一个。该装置还包括第二柔性层。第二柔性层包括基本平行于第二表面并面向第二表面的第三表面。第二柔性层还包括第四表面。该装置还包括附着到第三表面的电压参考平面。电压参考迹线和电压参考平面之间形成互连。

3. 发明申请

WO2018125443A1 MULTI-CONDUCTOR INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE 审中-公开
公开(公告)号：WO2018125443A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/062973
申请日：2017-11-22
申请人： INTEL CORPORATION
发明人： OOI, Ping Ping , CHEAH, Bok Eng , KONG, Jackson Chung Peng , OOI, Kooi Chi
IPC分类号： H01L25/065 , H01L23/485 , H01L23/00
摘要： A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

4. 发明申请

WO2017078717A1 STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE 审中-公开
标题翻译：采用电压基准面的堆叠封装组件
公开(公告)号：WO2017078717A1
公开(公告)日：2017-05-11
申请号：PCT/US2015/059191
申请日：2015-11-05
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KONG, Jackson, Chung Peng , OOI, Ping Ping , OOI, Kooi Chi , PERIAMAN, Shanggar
IPC分类号： H01L25/065 , H01L25/07 , H01L23/48
CPC分类号： H01L24/20 , H01L21/568 , H01L23/552 , H01L24/19 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
摘要翻译：本公开的实施例针对用于嵌入式裸片的堆叠封装组件以及相关技术和配置。在一个实施例中，堆叠封装组件可以包括彼此堆叠的第一管芯封装和第二管芯封装，其间具有多个互连; 以及嵌入第一和第二管芯封装中的至少一个中的电压参考平面，所述电压参考平面接近且大致平行于第一和第二管芯封装中的另一个。

5. 发明申请

WO2014003533A1 MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME 审中-公开
标题翻译：具有中间垂直侧芯片和半导体封装的多芯半导体结构
公开(公告)号：WO2014003533A1
公开(公告)日：2014-01-03
申请号：PCT/MY2012/000191
申请日：2012-06-25
申请人： INTEL CORPORATION , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , KONG, Jackson Chung Peng
发明人： CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , KONG, Jackson Chung Peng
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译：描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。还包括具有半导体管芯的第二基本水平布置的第二MSD结构。中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。

6. 发明申请

WO2018125679A1 SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH 审中-公开
公开(公告)号：WO2018125679A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/067366
申请日：2017-12-19
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , CHEAH, Bok Eng , OOI, Ping Ping , OOI, Kooi Chi
IPC分类号： H05K1/02 , H05K1/11
摘要： An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

7. 发明申请

WO2016209529A1 ELECTROSTATIC DISCHARGE FOR ELECTRONIC DEVICE COUPLING 审中-公开
标题翻译：用于电子设备耦合的静电放电
公开(公告)号：WO2016209529A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/034343
申请日：2016-05-26
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , CHEN, Kuan-Yu , CHEAH, Bok Eng , KOH, Boon Ping , TANG, Min Keen , HECK, Howard L. , OOI, Kooi Chi
IPC分类号： H01R13/648 , H01R13/652 , H01R13/22
CPC分类号： H01R13/6485 , H05K9/0067
摘要： In one example an electronic device comprises a housing, a receptacle in the housing comprising an opening at a distal end to receive a plug, a data connector positioned in the receptacle to provide a communication connection, and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly comprises a dedicated discharge path and a conductive pin mounted on a retention latch and moveable between a first position in which the conductive pin is in electrical contact with the data connector and a second position in which the conductive pin is not in electrical contact with the data connector. Other examples may be described.
摘要翻译：在一个示例中，电子设备包括壳体，壳体中的插座，包括在远端处的接收插头的开口，位于插座中的数据连接器以提供通信连接，以及定位在开口附近的静电导体组件插座，其中所述静电导体组件包括专用放电路径和安装在保持闩锁上的导电针，并且可在所述导电针与所述数据连接器电接触的第一位置和在所述第二位置之间移动的第二位置，不与数据连接器电接触。可以描述其他示例。

8. 发明申请

WO2016118276A1 ELECTROSTATIC DISCHARGE FOR ELECTRONIC DEVICE COUPLING 审中-公开
标题翻译：用于电子设备耦合的静电放电
公开(公告)号：WO2016118276A1
公开(公告)日：2016-07-28
申请号：PCT/US2015/066853
申请日：2015-12-18
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , CHEAH, Bok Eng , HECK, Howard, L. , CHEN, Kuan-Yui , KOH, Boon Ping , TANG, Min Keen , OOI, Kooi Chi
IPC分类号： H01R13/648 , H01R24/60
CPC分类号： H01R13/6485 , H01R24/66 , H01R2107/00
摘要： In one example an electronic device comprises a housing. A receptacle in the housing comprising an opening at a distal end to receive a plug and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly is coupled to a dedicated electrical discharge path. Other examples may be described.
摘要翻译：在一个示例中，电子设备包括壳体。壳体中的容器包括在远端处的开口，用于容纳插头和邻近插座中的开口定位的静电导体组件，其中静电导体组件耦合到专用放电路径。可以描述其他示例。

9. 发明申请

WO2016074176A1 FLEXIBLE SYSTEM-IN-PACKAGE SOLUTIONS FOR WEARABLE DEVICES 审中-公开
标题翻译：用于可穿戴设备的灵活的系统级封装解决方案
公开(公告)号：WO2016074176A1
公开(公告)日：2016-05-19
申请号：PCT/CN2014/090939
申请日：2014-11-12
申请人： INTEL CORPORATION , TANG, Jiamiao , ZHAO, Junfeng , SKINNER, Michael P. , SHE, Yong , SIR, Jiun Hann , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , CHEW, Yen Hsiang
发明人： TANG, Jiamiao , ZHAO, Junfeng , SKINNER, Michael P. , SHE, Yong , SIR, Jiun Hann , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , CHEW, Yen Hsiang
IPC分类号： H01L23/28
CPC分类号： G06F1/163 , A41B1/00 , A41D1/06 , A41D1/08 , A41F9/002 , A43B3/001 , A43B3/0015 , A43B7/141 , A44C5/0015 , A44C15/005 , F03G5/06 , G06F1/189 , H01L21/4853 , H01L21/565 , H01L23/3135 , H01L23/49838 , H01L23/4985 , H01L23/562 , H01L25/0655 , H01L25/50 , H01L2224/16225 , H01L2224/48091 , H01L2224/73257 , H01L2924/0002 , H01L2924/181 , H02J1/14 , H05K1/189 , H05K2201/05 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate (102). The flexible substrate (102) may have a plurality of dies (104 -112) coupled therewith. The IC package may include a first encapsulation material (116-120), having a first rigidity, disposed on the flexible substrate (102) to at least partially encapsulate each die of the plurality dies (104 -112). The IC package may further include a second encapsulation material (122), having a second rigidity, disposed on the flexible substrate (102). In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及集成电路（IC）封装。在实施例中，集成电路（IC）封装可以包括柔性基板（102）。柔性基板（102）可以具有与其连接的多个管芯（104-112）。 IC封装可以包括具有第一刚性的第一封装材料（116-120），其设置在柔性基板（102）上以至少部分地封装多个管芯（104-112）中的每个管芯。 IC封装还可以包括设置在柔性基板（102）上的具有第二刚性的第二封装材料（122）。在实施例中，第二刚性和第一刚度彼此不同。可以描述和/或要求保护其他实施例。

10. 发明申请

WO2016048347A1 FLEXIBLE PACKAGING ARCHITECTURE 审中-公开
标题翻译：灵活的包装结构
公开(公告)号：WO2016048347A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057648
申请日：2014-09-26
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KONG, Jackson Chung Peng , PERIAMAN, Shanggar , SKINNER, Michael , CHEW, Yen Hsiang , MAR, Kheng Tat , ABD RAZAK, Ridza Effendi , OOI, Kooi Chi
IPC分类号： H01L23/12
CPC分类号： H01L23/5387 , H01L21/4846 , H01L23/5389 , H01L24/19 , H01L25/0652 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/24137 , H01L2224/73259 , H01L2924/15311
摘要： A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.
摘要翻译：描述了适用于弯曲包装形状的柔性包装结构。在一个示例中，封装具有第一裸片，第一裸片上的第一模具化合物层，第一模具化合物层上方的布线层，布线层上的第二裸片，并且电耦合到布线层，以及第二模具化合物层叠在第二个模具上。

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