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1. 发明申请

US20150318375A1 SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS & ENHANCEMENT MODE OPERATION 有权
标题翻译：自对准结构和非对称GAN晶体管和增强模式运行的方法
公开(公告)号：US20150318375A1
公开(公告)日：2015-11-05
申请号：US14752365
申请日：2015-06-26
申请人： Intel Corporation
发明人： Sansaptak Dasgupta , Han Wui THEN , Marko RADOSAVLJEVIC , Niloy MUKHERJEE , Niti GOEL , Sanaz Kabehie GARDNER , Seung Hoon SUNG , Ravi PILLARISETTY , Robert S. CHAU
IPC分类号： H01L29/66 , H01L29/205 , H01L21/223 , H01L21/02 , H01L29/08 , H01L21/265 , H01L29/20 , H01L21/311
CPC分类号： H01L29/7784 , H01L21/0254 , H01L21/2233 , H01L21/2236 , H01L21/2654 , H01L21/26546 , H01L21/31111 , H01L21/31144 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42376 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
摘要翻译：实施例包括高电子迁移率晶体管（HEMT）。在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

2. 发明申请

US20170256408A1 METHODS AND STRUCTURES TO PREVENT SIDEWALL DEFECTS DURING SELECTIVE EPITAXY 审中-公开
公开(公告)号：US20170256408A1
公开(公告)日：2017-09-07
申请号：US15604550
申请日：2017-05-24
申请人： Intel Corporation
发明人： Niloy MUKHERJEE , Niti GOEL , Sanaz K. GARDNER , Pragyansri PATHI , Matthew V. METZ , Sansaptak DASGUPTA , Seung Hoon SUNG , James M. POWERS , Gilbert DEWEY , Benjamin CHU-KUNG , Jack T. KAVALIEROS , Robert S. CHAU
IPC分类号： G06Q30/02
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/02516 , H01L21/02532 , H01L21/02538 , H01L21/02609 , H01L21/02636 , H01L21/02639 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/8258 , H01L27/0924 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/7848
摘要： Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

3. 发明申请

US20160181099A1 METHODS AND STRUCTURES TO PREVENT SIDEWALL DEFECTS DURING SELECTIVE EPITAXY 有权
标题翻译：在选择性外延期间防止边墙缺陷的方法和结构
公开(公告)号：US20160181099A1
公开(公告)日：2016-06-23
申请号：US14908987
申请日：2013-09-04
申请人： INTEL CORPORATION
发明人： Niloy MUKHERJEE , Niti GOEL , Sanaz K. GARDNER , Pragyansri PATHI , Matthew V. METZ , Sansaptak DASGUPTA , Seung Hoon SUNG , James M. POWERS , Gilbert DEWEY , Benjamin CHU-KUNG , Jack T. KAVALIEROS , Robert S. CHAU
IPC分类号： H01L21/02 , H01L27/092 , H01L29/08 , H01L29/78 , H01L29/165 , H01L29/04 , H01L29/06 , H01L21/8238 , H01L29/267
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/02516 , H01L21/02532 , H01L21/02538 , H01L21/02609 , H01L21/02636 , H01L21/02639 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/8258 , H01L27/0924 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/7848
摘要： Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (I) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
摘要翻译：提供沟槽（以及用于形成沟槽的工艺），其从衬底材料的顶表面减少或防止III-V族或锗（Ge）材料（例如，“缓冲材料”）的选择性外延生长中的晶体缺陷。缺陷可能由选择性外延侧壁生长与氧化物沟槽侧壁的碰撞引起。这种沟槽包括（I）相对于衬底表面以40度至70度（例如55度）之间的角度具有倾斜侧壁的沟槽; 和/或（2）具有在下沟槽的开口上方并且围绕下沟槽（例如，下沟槽可以具有倾斜侧壁，短垂直壁或高垂直壁）的上沟槽的组合沟槽。这些沟槽减少或防止外延侧壁生长中的缺陷，其中生长与其生长的沟槽的垂直侧壁接触或生长。

4. 发明申请

US20190088747A1 SELECTIVE EPITAXIALLY GROWN III-V MATERIALS BASED DEVICES 审中-公开
公开(公告)号：US20190088747A1
公开(公告)日：2019-03-21
申请号：US16198725
申请日：2018-11-21
申请人： Intel Corporation
发明人： Niti GOEL , Gilbert DEWEY , Niloy MUKHERJEE , Matthew V. METZ , Marko RADOSAVLIJEVIC , Benjamin CHU-KUNG , Jack T. KAVALIEROS , Robert S. CHAU
IPC分类号： H01L29/205 , H01L29/66 , H01L29/78 , H01L21/02 , H01L29/06 , H01L29/20
摘要： A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

5. 发明申请

US20170148728A1 DECOUPLING CAPACITORS AND ARRANGEMENTS 有权
公开(公告)号：US20170148728A1
公开(公告)日：2017-05-25
申请号：US15125964
申请日：2014-06-27
申请人： Intel Corporation
发明人： Silvio E. BOU-GHAZALE , Rany T. ELSAYED , Niti GOEL
IPC分类号： H01L23/522 , H01L49/02 , H01L27/06
CPC分类号： H01L23/5223 , H01L27/0629 , H01L27/0733 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.

6. 发明申请

US20160211263A1 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY 有权
标题翻译：通过选择性和合格外观组合的CMOS图案化硅基板上的非硅器件杂质
公开(公告)号：US20160211263A1
公开(公告)日：2016-07-21
申请号：US14915185
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： Niti GOEL , Robert S. CHAU , Jack T. KAVALIEROS , Benjamin CHU-KUNG , Matthew V. METZ , Niloy MUKHERJEE , Nancy M. ZELICK , Gilbert DEWEY , Willy RACHMADY , Marko RADOSAVLJEVIC , Van H. LE , Ravi PILLARISETTY , Sansaptak DASGUPTA
IPC分类号： H01L27/092 , H01L29/06 , H01L29/205 , H01L21/8238 , H01L21/8252 , H01L29/165 , H01L29/66 , H01L21/02
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02598 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8252 , H01L27/0922 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66795 , H01L29/785
摘要： A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
摘要翻译：从形成在浅沟槽隔离（STI）区域之间的一个或一对沟槽的底部的衬底表面外延生长单个鳍或一对共同组合的n型和p型单晶电子器件鳍。翅片或翅片被图案化并且STI区域被蚀刻以形成在STI区域的蚀刻顶表面之上延伸的翅片或翅片的高度。翅片高度可以是其宽度的至少1.5倍。暴露的侧壁表面和每个翅片的顶表面用一个或多个共形外延材料外延包层以在翅片上形成器件层。在生长翅片之前，可以从衬底表面生长毯式缓冲外延材料; 并且生长在STI沟槽中的翅片形成在覆盖层上方。翅片的这种形成减少了材料界面晶格失配的缺陷。

7. 发明申请

US20160204263A1 IMPROVED CLADDING LAYER EPITAXY VIA TEMPLATE ENGINEERING FOR HETEROGENEOUS INTEGRATION ON SILICON 审中-公开
标题翻译：通过模具工程改进粘合层外延在硅中的异质整合
公开(公告)号：US20160204263A1
公开(公告)日：2016-07-14
申请号：US14914906
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： Niloy MUKHERJEE , Marko RADOSAVLJEVIC , Jack T. KAVALIEROS , Ravi PILLARISETTY , Niti GOEL , Van H. LE , Gilbert DEWEY , Benjamin CHU-KUNG
IPC分类号： H01L29/78 , H01L29/06 , H01L21/02 , H01L29/66
摘要： An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.
摘要翻译：一种包括半导体本体的装置，包括沟道区和设置在沟道区的相对侧上的结区，所述半导体本体包括包括第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及设置在通道区域上的栅极堆叠。一种方法，包括在衬底上方的分开的平面中形成多个纳米线，所述多个纳米线中的每一个包括包括第一带隙的材料; 在所述多个纳米线的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 并在所述包层材料上设置栅极叠层。

8. 发明申请

US20160204208A1 SELECTIVE EPITAXIALLY GROWN III-V MATERIALS BASED DEVICES 有权
标题翻译：选择性外形III-V材料的设备
公开(公告)号：US20160204208A1
公开(公告)日：2016-07-14
申请号：US14778574
申请日：2013-06-28
申请人： Intel Corporation
发明人： Niti GOEL , Gilbert DEWEY , Niloy MUKHERJEE , Matthew V. METZ , Marko RADOSAVLJEVIC , Benjamin CHU-KUNG , Jack T. KAVALIEROS , Robert S. CHAU
IPC分类号： H01L29/205 , H01L29/06 , H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L29/205 , H01L21/02381 , H01L21/02463 , H01L21/02466 , H01L21/02502 , H01L21/02538 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L29/0607 , H01L29/20 , H01L29/66469 , H01L29/66522 , H01L29/66795 , H01L29/785
摘要： A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
摘要翻译：第一种基于III-V材料的缓冲层沉积在硅衬底上。第二个III-V材料的缓冲层沉积在第一个III-V材料的缓冲层上。在基于第二III-V材料的缓冲层上沉积基于III-V材料的器件沟道层。

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