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1. 发明申请

WO2017164872A1 SYSTEM-ON-CHIP DEVICES AND METHODS FOR TESTING SYSTEM-ON-CHIP DEVICES 审中-公开
标题翻译：片上系统设备和用于测试片上系统设备的方法
公开(公告)号：WO2017164872A1
公开(公告)日：2017-09-28
申请号：PCT/US2016/023866
申请日：2016-03-24
申请人： INTEL CORPORATION
发明人： LI, Wei
IPC分类号： G01R31/317 , G01R31/3181 , G01R31/3183 , G01R31/3187
摘要： A system-on-chip device includes a first circuit configured to operate in a first clock domain and a second circuit configured to operate in a second clock domain. A clock frequency of the first clock domain is higher than a clock frequency of the second clock domain in a first operating state of the system-on-chip device. Further, the system-on-chip device includes an input/output interface circuit configured to receive input signals from the first circuit and provide corresponding output signals to the second circuit and configured to receive input signals from the second circuit and provide corresponding output signals to the first circuit. Additionally, the system-on-chip device includes a test circuit connected to the input/output interface circuit and configured to at least one of providing a test input signal to the in¬ put/output interface circuit and receiving a test output signal from the input/output interface circuit in a test mode of the system-on-chip device.
摘要翻译：芯片上系统装置包含经配置以在第一时钟域中操作的第一电路以及经配置以在第二时钟域中操作的第二电路。在片上系统设备的第一操作状态下，第一时钟域的时钟频率高于第二时钟域的时钟频率。此外，片上系统设备包括输入/输出接口电路，其被配置为接收来自第一电路的输入信号并将对应的输出信号提供给第二电路并且被配置为接收来自第二电路的输入信号并将对应的输出信号提供给第一个电路。另外，片上系统设备包括连接到输入/输出接口电路并且被配置为将测试输入信号提供给输入/输出接口电路中的至少一个的测试电路。放置/输出接口电路，并且在片上系统设备的测试模式下从输入/输出接口电路接收测试输出信号。

2. 发明申请

WO2017107122A1 TECHNIQUES FOR COORDINATING DEVICE BOOT SECURITY 审中-公开
标题翻译：协调设备引导安全的技术
公开(公告)号：WO2017107122A1
公开(公告)日：2017-06-29
申请号：PCT/CN2015/098651
申请日：2015-12-24
申请人： INTEL CORPORATION , YAO, Jiewen , ZIMMER, Vincent J. , LI, Wei , POORNACHANDRAN, Rajesh , MUDUSURU, Giri P.
发明人： YAO, Jiewen , ZIMMER, Vincent J. , LI, Wei , POORNACHANDRAN, Rajesh , MUDUSURU, Giri P.
IPC分类号： G06F21/57
CPC分类号： G06F21/57 , G06F21/575
摘要： Techniques for providing and maintaining protection of firmware routines that form part of a chain of trust through successive processing environments. An apparatus may include a first processor component (550); a volatile storage (562) coupled to the first processor component; an enclave component to, in a pre-OS operating environment, generate a secure enclave within a portion of the volatile storage to restrict access to a secured firmware loaded into the secure enclave; a first firmware driver (646) to, in the pre-OS operating environment, provide a first API to enable unsecured firmware to call a support routine of the secured firmware from outside the secure enclave; and a second firmware driver (647) to, in an OS operating environment that replaces the pre-OS operating environment, provide a second API to enable an OS of the OS operating environment to call the support routine from outside the secure enclave.
摘要翻译：通过连续处理环境提供并维护构成信任链一部分的固件例程的保护技术。一种装置可以包括第一处理器组件（550）; 耦合到第一处理器组件的易失性存储器（562）用于在OS前操作环境中在易失性存储器的一部分内生成安全区域以限制对加载到安全区域中的安全固件的访问的区域组件; 第一固件驱动程序（646），用于在OS前操作环境中提供第一API以使得不安全固件能够从安全区域外部调用安全固件的支持例程; 以及第二固件驱动程序（647），用于在替换操作系统前操作环境的操作系统操作环境中提供第二API以使操作系统操作环境的操作系统能够从安全飞地外调用支持例程。 p>

3. 发明申请

WO2013101069A1 CORE SWITCHING ACCELARATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：不对称多处理器系统中的核心切换加速
公开(公告)号：WO2013101069A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067851
申请日：2011-12-29
申请人： INTEL CORPORATION , YAMADA, Koichi , GINZBURG, Boris , LI, Wei , RONEN, Ronny , NATANZON, Esfir , LEVIT-GUREVICH, Konstantin , HABER, Gadi , NAVEH, Alon , WEISSMANN, Eliezer , MISHAELI, Michael
发明人： YAMADA, Koichi , GINZBURG, Boris , LI, Wei , RONEN, Ronny , NATANZON, Esfir , LEVIT-GUREVICH, Konstantin , HABER, Gadi , NAVEH, Alon , WEISSMANN, Eliezer , MISHAELI, Michael
IPC分类号： G06F9/30 , G06F9/44 , G06F15/80
CPC分类号： G06F9/30181 , G06F9/5044 , G06F9/5094 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。可以进行选择以提供程序代码的本地执行，以最小化功耗等等。可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。然后由ASMP执行检测的程序代码。

4. 发明申请

WO2006036504A3 SYSTEM, METHOD AND APPARATUS FOR DEPENDENCY CHAIN PROCESSING 审中-公开
公开(公告)号：WO2006036504A3
公开(公告)日：2006-04-06
申请号：PCT/US2005/032118
申请日：2005-09-12
申请人： INTEL CORPORATION
发明人： NARAYANASAMY, Satish , WANG, Hong , SHEN, John , ROSNER, Roni , ALMOG, Yoav , SCHWARTZ, Naftali , HOFLEHNER, Gerolf , LAVERY, Daniel , LI, Wei , TIAN, Xinmin , GIRKAR, Milind , WANG, Perry
IPC分类号： G06F9/45
摘要： Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is adapted to accommodate a size of the dependency chains; and/or processing in parallel a plurality of dependency chains of a trace. Other embodiments are described and claimed.

5. 发明申请

WO2013100996A1 BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：不对称多处理器系统中的二进制翻译
公开(公告)号：WO2013100996A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067654
申请日：2011-12-28
申请人： INTEL CORPORATION , YAMADA, Koichi , RONEN, Ronny , LI, Wei , GINZBURG, Boris , HABER, Gadi , LEVIT-GUREVICH, Konstantin (kostya) , NATANZON, Esfir , NAVEH, Alon , WEISSMANN, Eliezer , MISHAELI, Michael
发明人： YAMADA, Koichi , RONEN, Ronny , LI, Wei , GINZBURG, Boris , HABER, Gadi , LEVIT-GUREVICH, Konstantin (kostya) , NATANZON, Esfir , NAVEH, Alon , WEISSMANN, Eliezer , MISHAELI, Michael
IPC分类号： G06F15/80 , G06F9/30 , G06F9/44 , G06F1/32
CPC分类号： G06F9/30145 , G06F1/3243 , G06F1/3293 , G06F9/30174 , G06F9/3808 , G06F9/4552 , G06F9/5094 , G06F15/7807 , Y02D10/122 , Y02D10/152 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。分析用于在ASMP上执行的程序代码，并且确定是否允许程序代码或其代码段在本地上在第一核上执行或者对代码使用二进制转换并且在在执行过程中消耗的功率比第一个核心少的第二个核心。

6. 发明申请

WO2016160204A1 APPLICATION CONTAINER FOR LIVE MIGRATION OF MOBILE APPLICATIONS 审中-公开
标题翻译：移动应用移动应用集装箱
公开(公告)号：WO2016160204A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/019774
申请日：2016-02-26
申请人： INTEL CORPORATION , DAS, Abhinav , SHUKLA, Saurabh S. , LI, Wei , LAVERY, Daniel M.
发明人： DAS, Abhinav , SHUKLA, Saurabh S. , LI, Wei , LAVERY, Daniel M.
IPC分类号： G06F9/54 , G06F9/44
CPC分类号： G06F9/45558 , G06F9/4484 , G06F9/45504 , G06F9/4856 , G06F2009/4557 , G06F2009/45595
摘要： Systems, apparatuses and methods may provide for isolating native information from non-native information, wherein the native information is associated with a mobile application running in a managed runtime environment. Additionally, the native information may be checkpointed and transferred from a first device to a second device in response to a live migration event. In one example, the native information includes native code and native state data and isolating the native information from the non-native information includes dispatching one or more native function calls to a binary translation (BT) container that manages a memory pool dedicated to the native information.
摘要翻译：系统，装置和方法可以提供将本机信息与非本地信息隔离开，其中本地信息与在受管理的运行时环境中运行的移动应用相关联。此外，响应于实时迁移事件，本地信息可以被检查点并从第一设备传送到第二设备。在一个示例中，本地信息包括本地代码和本地状态数据，并且从非本机信息隔离本机信息包括将一个或多个本地函数调用分派到二进制翻译（BT）容器，二进制翻译（BT）容器管理专用于本地信息。

7. 发明申请

WO2011159739A2 REGISTER MAPPING TECHNIQUES FOR EFFICIENT DYNAMIC BINARY TRANSLATION 审中-公开
标题翻译：用于有效动态二进制翻译的注册映射技术
公开(公告)号：WO2011159739A2
公开(公告)日：2011-12-22
申请号：PCT/US2011/040406
申请日：2011-06-14
申请人： INTEL CORPORATION , OTTONI, Guilherme D. , WANG, Hong , LI, Wei
发明人： OTTONI, Guilherme D. , WANG, Hong , LI, Wei
IPC分类号： G06F9/45 , G06F9/30 , G06F9/24
CPC分类号： G06F8/441 , G06F9/45525
摘要： Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region.
摘要翻译：通常，本公开提供了一种用于将具有更多寄存器的系统的寄存器映射到具有较少寄存器的系统的系统和方法。可以形成包括具有相对频繁的寄存器访问的一个或多个代码块的区域。最常访问的源寄存器可能被映射到目标寄存器。该区域中的每个块可以由前序和至少一个结尾界定。序言可以被配置为实现寄存器映射，并且结尾可以被配置为管理从该区域中的块到该区域中的另一块或者不在该区域中的块的程序流。

8. 发明申请

WO2007041122A1 THREAD-DATA AFFINITY OPTIMIZATION USING COMPILER 审中-公开
标题翻译：使用编译器的线程优化优化
公开(公告)号：WO2007041122A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/037576
申请日：2006-08-26
申请人： INTEL CORPORATION , TIAN, Xinmin , GIRKAR, Milind , SHER, David , GROVE, Richard , LI, Wei , WANG, Hong , NEWBURN, Chris , WANG, Perry , SHEN, John
发明人： TIAN, Xinmin , GIRKAR, Milind , SHER, David , GROVE, Richard , LI, Wei , WANG, Hong , NEWBURN, Chris , WANG, Perry , SHEN, John
IPC分类号： G06F9/45
CPC分类号： G06F8/45
摘要： Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is then compiled in a first pass and executed. During execution, the compiler collects profiling data using a profiling tool. Then, in a second pass, the compiler performs thread-data affinity optimization on the program using the collected profiling data.
摘要翻译：线程数据亲和度优化可以在编译要在高速缓存相干非均匀内存访问（cc-NUMA）平台上执行的计算机程序时由编译器执行。在一个实施例中，本发明包括接收要编译的程序。接收的程序然后被编译成第一遍并被执行。在执行期间，编译器使用分析工具收集分析数据。然后，在第二遍，编译器使用收集的分析数据对程序执行线程数据关联优化。

9. 发明公开

EP4109153A1 BARRIERS FOR GROOVES IN PHOTONICS DIES 审中-实审
公开(公告)号：EP4109153A1
公开(公告)日：2022-12-28
申请号：EP22150658.7
申请日：2022-01-10
申请人： INTEL Corporation
发明人： LI, Xiaoqian , LI, Wei , SHAW, Santosh , HUANG, Jingyi
IPC分类号： G02B6/36 , G02B6/42
摘要： Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package includes a photonics die and a plurality of v-grooves on the photonics die. A barrier structure proximate the plurality of v-grooves.

10. 发明公开

EP1949227A1 THREAD-DATA AFFINITY OPTIMIZATION USING COMPILER 审中-公开
标题翻译：线程数据AFFINITY优化利用编译器
公开(公告)号：EP1949227A1
公开(公告)日：2008-07-30
申请号：EP06825144.6
申请日：2006-08-26
申请人： Intel Corporation
发明人： TIAN, Xinmin , GIRKAR, Milind , SHER, David , GROVE, Richard , LI, Wei , WANG, Hong , NEWBURN, Chris , WANG, Perry , SHEN, John
IPC分类号： G06F9/45
CPC分类号： G06F8/45
摘要： Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is then compiled in a first pass and executed. During execution, the compiler collects profiling data using a profiling tool. Then, in a second pass, the compiler performs thread-data affinity optimization on the program using the collected profiling data.

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