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1. 发明授权

US11899615B2 Multiple dies hardware processors and methods 有权
公开(公告)号：US11899615B2
公开(公告)日：2024-02-13
申请号：US18102568
申请日：2023-01-27
申请人： Intel Corporation
发明人： Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z Chrysos , John R. Ayers , Dheeraj R. Subbareddy
IPC分类号： G06F1/00 , G06F15/78 , G06F1/10 , G06F15/167 , G06F1/04 , G06F1/12 , G06F9/38 , G06F9/50 , G06F15/173
CPC分类号： G06F15/7889 , G06F1/04 , G06F1/10 , G06F1/12 , G06F9/3869 , G06F9/5038 , G06F15/167 , G06F15/17312
摘要： Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

2. 发明授权

US10936490B2 System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms 有权
公开(公告)号：US10936490B2
公开(公告)日：2021-03-02
申请号：US15634785
申请日：2017-06-27
申请人： Intel Corporation
发明人： Andrew J. Herdrich , Edwin Verplanke , Stephen R. Van Doren , Ravishankar Iyer , Eric R. Wehage , Rupin H. Vakharwala , Rajesh M. Sankaran , Jeffrey D. Chamberlain , Julius Mandelblat , Yen-Cheng Liu , Stephen T. Palermo , Tsung-Yuan C. Tai
IPC分类号： G06F12/08 , G06F12/0811 , G06F13/42 , G06F9/455 , G06F9/50 , G06F12/1009 , G06F13/16
摘要： Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

3. 发明授权

US09418009B2 Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory 有权
标题翻译：本地缓存行的包含和非包容性跟踪，以避免缓存行内存上的近似存储器读取写入两级系统内存
公开(公告)号：US09418009B2
公开(公告)日：2016-08-16
申请号：US14142045
申请日：2013-12-27
申请人： Intel Corporation
发明人： Adrian C. Moga , Vedaraman Geetha , Bahaa Fahim , Robert G. Blankenship , Yen-Cheng Liu , Jeffrey D. Chamberlain , Stephen R. Van Doren
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0811 , G06F12/0888
摘要： A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.
摘要翻译：处理器可以包括与具有近存储器和远存储器的系统存储器接口的存储器控制器。处理器可以包括逻辑电路，以使存储器控制器确定写入请求是远程生成还是本地生成，并且当写入请求被远程生成以指示存储器控制器在执行写入之前执行近似存储器的读取，当写入请求在本地生成，并且由写入请求所针对的高速缓存行处于包含状态，以指示存储器控制器执行写入而不执行近似存储器的读取，并且当本地生成写入请求时，写请求处于非包容状态，以指示存储器控制器在执行写操作之前读取存储器。

4. 发明授权

US09921989B2 Method, apparatus and system for modular on-die coherent interconnect for packetized communication 有权
公开(公告)号：US09921989B2
公开(公告)日：2018-03-20
申请号：US14707656
申请日：2015-05-08
申请人： Intel Corporation
发明人： Krishnakumar Ganapathy , Yen-Cheng Liu , Antonio Juan , Steven R. Page , Jeffrey D. Chamberlain , Pau Cabre , Bahaa Fahim , Gunnar Gaubatz
IPC分类号： G06F13/00 , G06F13/40 , G06F15/78 , G06F13/42 , G06F9/44
CPC分类号： G06F13/4022 , G06F9/4411 , G06F13/4036 , G06F13/4068 , G06F13/4282 , G06F15/7825
摘要： In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

5. 发明授权

US09207753B2 Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline 有权
标题翻译：多重队列多资源进入睡眠和唤醒功能，节省了基于重试的管道中的带宽保持
公开(公告)号：US09207753B2
公开(公告)日：2015-12-08
申请号：US14519584
申请日：2014-10-21
申请人： Intel Corporation
发明人： James R. Vash , Pritpal S. Ahuja , Bongjin Jung , Jeffrey D. Chamberlain
IPC分类号： G06F1/32 , G06F13/00 , G06F13/16 , H04L29/00
CPC分类号： G06F1/3293 , G06F13/00 , G06F13/1642 , H04L29/00 , Y02D10/14
摘要： Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.
摘要翻译：描述了在基于重试的流水线中与多队列多资源进入睡眠和唤醒功率节省和带宽保持有关的方法和装置。在一个实施例中，一位指示相应的队列条目是否相对于基于重试的流水线中的资源的仲裁而睡眠或唤醒。此外，来自不同队列的多个条目可以被分组在一起，并且多个资源可以被分组在一起。还公开了其他实施例。

6. 发明授权

US11966330B2 Link affinitization to reduce transfer latency 有权
公开(公告)号：US11966330B2
公开(公告)日：2024-04-23
申请号：US16894402
申请日：2020-06-05
申请人： Intel Corporation
发明人： Vinit Mathew Abraham , Jeffrey D. Chamberlain , Yen-Cheng Liu , Eswaramoorthi Nallusamy , Soumya S. Eachempati
IPC分类号： G06F13/16 , G06F12/08 , G06F12/0802 , G06F13/40
CPC分类号： G06F12/0802 , G06F13/1668 , G06F13/4027 , G06F2213/16 , G06F2213/40
摘要： Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.

7. 发明授权

US11294852B2 Multiple dies hardware processors and methods 有权
公开(公告)号：US11294852B2
公开(公告)日：2022-04-05
申请号：US16917888
申请日：2020-06-30
申请人： Intel Corporation
发明人： Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z. Chrysos , John R. Ayers , Dheeraj R. Subbareddy
IPC分类号： G06F1/04 , G06F15/78 , G06F1/10 , G06F15/167 , G06F9/38 , G06F9/50 , G06F15/173
摘要： Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

8. 发明授权

US10140213B2 Two level memory full line writes 有权
公开(公告)号：US10140213B2
公开(公告)日：2018-11-27
申请号：US15447767
申请日：2017-03-02
申请人： Intel Corporation
发明人： Robert G. Blankenship , Jeffrey D. Chamberlain , Yen-Cheng Liu , Vedaraman Geetha
IPC分类号： G06F12/08 , G06F12/0891 , G06F12/0808 , G06F12/0831 , G06F12/0893 , G06F12/126
摘要： A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

9. 发明授权

US09606925B2 Method, apparatus and system for optimizing cache memory transaction handling in a processor 有权
公开(公告)号：US09606925B2
公开(公告)日：2017-03-28
申请号：US14669248
申请日：2015-03-26
申请人： Intel Corporation
发明人： Bahaa Fahim , Yen-Cheng Liu , Vedaraman Geetha , Jeffrey D. Chamberlain , Min Huang
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0855 , G06F12/0817 , G06F12/0831 , G06F2212/27 , G06F2212/621 , Y02D10/13
摘要： In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.

10. 发明授权

US09436605B2 Cache coherency apparatus and method minimizing memory writeback operations 有权
标题翻译：缓存一致性设备和最小化内存回写操作的方法
公开(公告)号：US09436605B2
公开(公告)日：2016-09-06
申请号：US14136131
申请日：2013-12-20
申请人： Intel Corporation
发明人： Jeffrey D. Chamberlain , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Adrian C. Moga , Herbert H. Hum , Sailesh Kottapalli
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815
摘要： An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.
摘要翻译：一种用于减少或消除写回操作的设备和方法。例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

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