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1. 发明申请

US20160179549A1 Instruction and Logic for Loop Stream Detection 审中-公开
标题翻译：循环流检测的指令和逻辑
公开(公告)号：US20160179549A1
公开(公告)日：2016-06-23
申请号：US14580498
申请日：2014-12-23
申请人： INTEL CORPORATION
发明人： POLYCHRONIS XEKALAKIS , JAMISON D. COLLINS , SUMIT AHUJA
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3818 , G06F9/3005 , G06F9/3842 , G06F9/3846
摘要： A processor includes a front end including a decoder to decode a branch instruction to perform a branch operation. The processor includes a loop stream unit with logic to identify from the branch instruction that the branch operation is a loop operation, determine whether the loop operation will include a fixed or effectively-infinite number of iterations, load decoded instructions of a loop iteration of the loop operation, and cyclically issue the decoded instructions of the loop iteration in a manner based upon whether the loop operation will include a fixed or effectively-infinite number of iterations. The processor also includes an execution unit to execute the branch instruction and a retirement unit including to retire the branch instruction.
摘要翻译：处理器包括前端，其包括用于解码分支指令以执行分支操作的解码器。处理器包括具有逻辑的循环流单元，用于从分支指令中识别分支操作是循环操作，确定循环操作是否包括固定或有效无限次数的迭代，将解码的指令循环迭代循环操作，并且基于循环操作是否将包括固定或无限次迭代次数的方式循环地发布循环迭代的解码指令。处理器还包括执行分支指令的执行单元和退出分支指令的退休单元。

2. 发明申请

US20160179538A1 METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PREDICATE VALUES WITH STACK SYNCHRONIZATION INSTRUCTIONS IN AN OUT OF ORDER HARDWARE SOFTWARE CO-DESIGNED PROCESSOR 审中-公开
标题翻译：用于通过订单硬件软件协同处理器实现堆栈同步指令来预测和维护预测值堆栈的方法和装置
公开(公告)号：US20160179538A1
公开(公告)日：2016-06-23
申请号：US14576915
申请日：2014-12-19
申请人： Intel Corporation
发明人： JAMISON D. COLLINS , Jayesh Iyer , Sebastian Winkel , Polychronis Xekalakis , Howard H. Chen , Rupert Brauch
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F8/41 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3013 , G06F9/30145 , G06F9/384 , G06F9/3859 , G06F9/3863
摘要： Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.
摘要翻译：用于使用堆栈同步指令来实现和维护谓词值堆栈的方法和装置的实施例。在一个实施例中，该装置是一种无序的硬件/软件协同设计的处理器，其包括明确地管理谓词寄存器堆栈以便在执行的分支之间保持堆栈一致性的指令，其将可变数量的谓词值推送到谓词堆栈。在一个实施例中，基于栈的谓词寄存器实现能够通过早期重命名谓词寄存器来实现早期分支计算和早期分支错误预测恢复。

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