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1. 发明公开

US20240006399A1 DIE-STACKED AND MOLDED ARCHITECTURE FOR MEMORY ON PACKAGE (MOP) 审中-公开
公开(公告)号：US20240006399A1
公开(公告)日：2024-01-04
申请号：US17853329
申请日：2022-06-29
申请人： Intel Corporation
发明人： Seok Ling Lim , Chan Kim Lee , Eng Huat Goh , Jenny Shio Yin Ong , Tin Poay Chuah
IPC分类号： H01L25/18 , H01L25/065 , H01L23/31 , H01L23/367 , H01L25/00 , H01L21/56 , H01L21/48 , H01L23/552
CPC分类号： H01L25/18 , H01L25/0652 , H01L23/3185 , H01L23/367 , H01L25/50 , H01L21/56 , H01L21/486 , H01L23/552 , H01L23/5386
摘要： An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.

2. 发明授权

US11096284B2 Compact semiconductor chip system and method 有权
公开(公告)号：US11096284B2
公开(公告)日：2021-08-17
申请号：US16451542
申请日：2019-06-25
申请人： Intel Corporation
发明人： Wee Hoe , Chan Kim Lee , Chee Chun Yee , Mooi Ling Chang , Siang Yeong Tan , Say Thong Tony Tan
IPC分类号： G06F1/16 , H05K1/18 , H01L25/16 , H01Q1/22 , H01L23/538
摘要： A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.

3. 发明授权

US11482481B2 Semiconductor device and system 有权
公开(公告)号：US11482481B2
公开(公告)日：2022-10-25
申请号：US16888155
申请日：2020-05-29
申请人： Intel Corporation
发明人： Bok Eng Cheah , Jackson Chung Peng Kong , Kooi Chi Ooi , Lee Fueng Yap , Chan Kim Lee
IPC分类号： H05K1/18 , H01L23/498 , H01L25/16 , H01L25/18
摘要： An electronic device is disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.

4. 发明授权

US09543244B2 Hybrid package transmission line circuits 有权
标题翻译：混合封装传输线路电路
公开(公告)号：US09543244B2
公开(公告)日：2017-01-10
申请号：US14543838
申请日：2014-11-17
申请人： Intel Corporation
发明人： Chung Peng Jackson Kong , Chang-Tsung Fu , Telesphor Kamgaing , Chan Kim Lee , Ping Ping Ooi
IPC分类号： H01L23/522 , H01L23/52 , H01L23/498 , H01L23/528
CPC分类号： H01L23/5226 , H01L23/49822 , H01L23/49827 , H01L23/528 , H01L2224/16
摘要： “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.
摘要翻译：描述了采用多个互连级别以跨越封装长度传播或返回单条信号线的“混合”传输线路电路。在封装传输线路电路实施例中，信号线在电耦合在一起的两个不同的互连级别中使用共同定位的迹线。在另外的实施例中，参考平面被提供在至少一个共定位轨迹的上方，下方或共面上。在实施例中，平衡信号线对包括作为传播信号线的两个相邻互连级别中的第一和第二同位置迹线，以及在两个相邻互连级别中的第三和第四同位序列作为具有接地平面Co 平面，和/或上方和/或下方两个相邻互连层。

5. 外观设计

USD759029S1 Computer on a stick 有权
标题翻译：电脑在棍子上
公开(公告)号：USD759029S1
公开(公告)日：2016-06-14
申请号：US29527683
申请日：2015-05-21
申请人： Intel Corporation
设计人： Howe Yin Loo , Greg A. La Tour , Chan Kim Lee , Bok Eng Cheah , Khai Ern See , Han Kung Chua , Chow Soon Lim , Choy Mei Yeow

6. 发明申请

US20210098350A1 RECESS BY-PASS INTERCONNECTS 有权
公开(公告)号：US20210098350A1
公开(公告)日：2021-04-01
申请号：US16888155
申请日：2020-05-29
申请人： Intel Corporation
发明人： Bok Eng Cheah , Jackson Chung Peng Kong , Kooi Chi Ooi , Lee Fueng Yap , Chan Kim Lee
IPC分类号： H01L23/498 , H01L25/16 , H01L25/18 , H05K1/18
摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.

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