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1. 发明申请

WO2014084902A1 MULTI-TRANSCEIVER WIRELESS COMMUNICATION DEVICE AND METHODS FOR ADAPTIVE MULTI-BAND COMMUNICATION 审中-公开
标题翻译：多收发器无线通信设备和自适应多通信通信的方法
公开(公告)号：WO2014084902A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/044110
申请日：2013-06-04
申请人： INTEL CORPORATION
发明人： CHEN, Huimin , HULL, Christopher , TETZLAFF, Thomas, A.
IPC分类号： H04W74/00 , H04W80/02 , H04L5/16
CPC分类号： H04L5/16 , H04L5/0053 , H04L5/14 , H04W84/12
摘要： Embodiments of a multi-transceiver wireless communication device and methods for adaptive multi-band communication are generally described herein. In some embodiments, the multi-transceiver wireless communication device is configurable for half-duplex operation and for asymmetrical full-duplex operation on two non-interfering channels. In some embodiments, a contention-based channel access procedure may be performed to attempt to gain access to both a primary channel and an auxiliary channel. A primary transceiver and an auxiliary transceiver may be configured for asymmetrical full-duplex operation when access to both the primary channel and the auxiliary channel is granted. One of the transceivers may be configured for half-duplex operation when access to only one of the channels is granted. During asymmetrical full-duplex operation, the primary transceiver may be configured to communicate data packets using the primary channel, and the auxiliary transceiver may be configured to communicate control packets using an auxiliary channel.
摘要翻译：多收发器无线通信装置的实施例和用于自适应多频带通信的方法在本文中一般地被描述。在一些实施例中，多收发器无线通信设备可配置用于半双工操作和用于两个非干扰信道上的非对称全双工操作。在一些实施例中，可以执行基于竞争的信道接入过程以试图获得对主信道和辅助信道的接入。当允许访问主信道和辅助信道时，主收发机和辅助收发机可被配置用于不对称全双工操作。其中一个收发器可以被配置为半双工操作，当仅允许访问仅一个信道时。在非对称全双工操作期间，主收发器可以被配置为使用主信道传送数据分组，并且辅助收发机可以被配置为使用辅助信道来传送控制分组。

2. 发明申请

WO2012161736A1 ASYMMETRIC LINK FOR STREAMING APPLICATIONS 审中-公开
标题翻译：流量应用的不对称链接
公开(公告)号：WO2012161736A1
公开(公告)日：2012-11-29
申请号：PCT/US2011/067006
申请日：2011-12-22
申请人： INTEL CORPORATION , CHEN, Huimin , QUIET, Duane G. , HARRIMAN, David J.
发明人： CHEN, Huimin , QUIET, Duane G. , HARRIMAN, David J.
IPC分类号： H04N7/24 , H04L7/00
CPC分类号： H04L7/00 , H04L7/033 , H04L25/4902 , H04N5/04 , H04N7/24
摘要： Systems and methods of supporting video streaming operations may involve transmitting a pulse width modulated (PWM) control signal to an imaging device, wherein the imaging devices identifies control data based on a duty cycle of the control signal. The imaging device can configure a video stream based on the control data and synchronize transmission of the video stream based on a frequency of the control signal.
摘要翻译：支持视频流操作的系统和方法可以涉及向成像设备发送脉宽调制（PWM）控制信号，其中成像设备基于控制信号的占空比识别控制数据。成像装置可以基于控制数据配置视频流，并基于控制信号的频率同步视频流的传输。

3. 发明申请

WO2014004903A1 EXPLICIT CONTROL MESSAGE SIGNALING 审中-公开
标题翻译：显示控制信息信号
公开(公告)号：WO2014004903A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/048313
申请日：2013-06-27
申请人： INTEL CORPORATION , CHEN, Huimin , CHANG, Kok Hong
发明人： CHEN, Huimin , CHANG, Kok Hong
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/385 , G06F1/3253 , G06F13/4072 , G06F13/4282 , G06F2213/0042 , H04L25/0272 , Y02D10/14 , Y02D10/151
摘要： A method for explicit control message signaling includes sending a single ended 1 signal on a pair of data lines, wherein the pair of data lines includes a first data line and a second data line. A voltage of the first data line is driven to a logic 1, while pulsing the voltage of the second data line between a logic 1 and a logic 0, wherein the pulses represent a control message.
摘要翻译：用于显式控制消息信令的方法包括在一对数据线上发送单端1信号，其中该对数据线包括第一数据线和第二数据线。第一数据线的电压被驱动到逻辑1，同时脉冲第二数据线的电压在逻辑1和逻辑0之间，其中脉冲表示控制消息。

4. 发明申请

WO2012040717A3 DIGITAL NRZI SIGNAL FOR SERIAL INTERCONNECT COMMUNICATIONS BETWEEN THE LINK LAYER AND PHYSICAL LAYER 审中-公开
公开(公告)号：WO2012040717A3
公开(公告)日：2012-03-29
申请号：PCT/US2011/053291
申请日：2011-09-26
申请人： INTEL CORPORATION , CHEN, Huimin , ZHANG, Chunyu , DURLEY, Paul, S.
发明人： CHEN, Huimin , ZHANG, Chunyu , DURLEY, Paul, S.
IPC分类号： H04L29/10 , H04L29/06 , G06F13/14
摘要： Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

5. 发明申请

WO2017160438A1 DISTRIBUTION OF FORWARDED CLOCK 审中-公开
标题翻译：前向时钟的分配
公开(公告)号：WO2017160438A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/017639
申请日：2017-02-13
申请人： INTEL CORPORATION
发明人： CHEN, Huimin
IPC分类号： G06F1/10 , G06F1/06
CPC分类号： H04L7/0008 , G06F13/40 , H04L7/0016 , H04L25/14
摘要： A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.
摘要翻译：源组件包括用于生成时钟信号的时钟源，用于在互连的多个数据通道上向宿组件发送信号的多个前端驱动器电路，以及时钟分配电路耦合到时钟源和多个前端驱动器电路。时钟分配电路用于在第一数据通道上分配时钟信号的第一时钟脉冲，并在第二数据通道上分配时钟信号的第二时钟脉冲。信宿部件用于恢复来自第一数据通道的时钟信号的第一时钟脉冲和来自第二数据通道的时钟信号的第二时钟脉冲，其中时钟恢复电路包括时钟重构逻辑以从第二数据通道重构时钟信号第一个时钟脉冲和第二个时钟脉冲。

6. 发明申请

WO2017112093A1 PTM FOR USB RETIMERS 审中-公开
标题翻译：适用于USB终端的PTM
公开(公告)号：WO2017112093A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/059932
申请日：2016-11-01
申请人： INTEL CORPORATION
发明人： MCGOWAN, Steven B. , CHEN, Huimin
IPC分类号： G06F13/38
CPC分类号： G06F13/36 , G06F13/4027 , G06F2213/0042 , H04L25/0298
摘要： A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a link delay management request on an upstream-facing port of the retimer. The method further includes receiving, at a downstream-facing port of the retimer, a link delay management request and responding to the request received on the downstream-facing port.
摘要翻译：
在通用串行总线系统中用重定时器进行精确时间管理的系统和方法。该方法包括从重定时器发起对重定时器的面向上游端口的链路延迟管理请求。该方法还包括在重定时器的面向下游的端口处接收链路延迟管理请求并且响应在面向下游端口上接收到的请求。

7. 发明申请

WO2017112046A1 DEVICE, METHOD AND SYSTEM FOR PERFORMING CLOSED CHASSIS DEBUG WITH A REPEATER 审中-公开
标题翻译：使用重复器来执行封闭机箱调试的设备，方法和系统
公开(公告)号：WO2017112046A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/056886
申请日：2016-10-13
申请人： INTEL CORPORATION , SRIVASTAVA, Amit Kumar , CHEN, Huimin
发明人： SRIVASTAVA, Amit Kumar , CHEN, Huimin
IPC分类号： G06F11/22 , G06F11/36
CPC分类号： G06F11/2294 , G06F11/36
摘要： Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.
摘要翻译：
与转发器交换调试信息的技术和机制以及平台的多路复用逻辑。在一个实施例中，多路复用逻辑可以被配置为包括第一模式的多种模式中的任一种，以在平台的中继器和调试客户端逻辑之间交换调试信息。多种模式中的另一种可以提供用于在中继器和平台的物理层接口之间交换除了任何调试信息之外的功能数据的替代通信路径。在另一个实施例中，中继器与由通用串行总线标准标识的中继器体系结构兼容。物理层接口与由相同通用总线标准标识的接口规范兼容。

8. 发明申请

WO2015199877A1 METHOD AND APPARATUS OF USB 3.1 RETIMER PRESENCE DETECT AND INDEX 审中-公开
标题翻译： USB 3.1退出存在检测和索引的方法和装置
公开(公告)号：WO2015199877A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/032664
申请日：2015-05-27
申请人： INTEL CORPORATION
发明人： CHEN, Huimin , HECK, Howard L.
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/423 , G05B2219/25181 , G06F13/4045 , G06F13/4256 , G06F2213/0052 , H04B3/58 , H04B10/29 , H04B2203/5479 , Y02B70/123 , Y02B70/126 , Y02D10/14 , Y02D10/151
摘要： An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.
摘要翻译：本文描述了重新定时器存在检测的装置。该装置包括至少一个重定时器，其中算法是使得至少一个重定时器通过在链路初始化期间断言存在消息的位来通知其存在。至少一个重定时器可以声明一个索引并且可以通过索引访问。

9. 发明申请

WO2014099524A1 RE-DRIVER POWER MANAGEMENT 审中-公开
标题翻译：再驱动电源管理
公开(公告)号：WO2014099524A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/074284
申请日：2013-12-11
申请人： INTEL CORPORATION , CHEN, Huimin , HECK, Howard L.
发明人： CHEN, Huimin , HECK, Howard L.
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3253 , G06F13/4004 , G06F13/4086 , Y02B70/126 , Y02D10/151
摘要： The present disclosure provides techniques for increasing the power efficiency of re-drivers by providing a technique for a re-driver to recognize a variety of power states. A message generator may be located in a host device and may encode a signal indicating a change in a power state. The message may be transmitted to a message decoder located in a re-driver. The message decoder may decode the message and the re-driver may enter a power state in response to the decoded message.
摘要翻译：本公开提供了通过提供用于重新驱动程序识别各种功率状态的技术来提高重新驱动器的功率效率的技术。消息发生器可以位于主机设备中，并且可以编码指示功率状态改变的信号。消息可以被发送到位于重新驱动器中的消息解码器。消息解码器可以对消息进行解码，并且重新驱动器可以响应于解码的消息而进入功率状态。

10. 发明申请

WO2014004925A1 A CLOCK-LESS HALF-DUPLEX REPEATER 审中-公开
标题翻译：无时钟双工重复机
公开(公告)号：WO2014004925A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/048363
申请日：2013-06-27
申请人： INTEL CORPORATION , CHEN, Huimin , CHANG, Kok Hong
发明人： CHEN, Huimin , CHANG, Kok Hong
IPC分类号： G06F13/14 , G06F13/42
CPC分类号： G06F13/4221 , G06F1/3296 , G06F13/4022 , G06F13/4027 , G06F2213/0042 , G06F2213/4004 , Y02D10/14 , Y02D10/151
摘要： A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.
摘要翻译：这里描述了用于在两个设备之间传送数据的方法和系统。该方法从中继器中的第一设备检测第一协议的电信号，其中第一协议包括单端信令。该方法还确定电信号的速度。此外，该方法基于电信号的速度将第一协议的电信号转换为第二协议的电信号。第二协议包括差分信令。此外，该方法将第二协议的电信号发送到第二设备。此外，当第二协议的电信号指示数据流的结束时，该方法将第二协议的电信号停止到第二设备。

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