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1. 发明申请

WO2012040717A3 DIGITAL NRZI SIGNAL FOR SERIAL INTERCONNECT COMMUNICATIONS BETWEEN THE LINK LAYER AND PHYSICAL LAYER 审中-公开
公开(公告)号：WO2012040717A3
公开(公告)日：2012-03-29
申请号：PCT/US2011/053291
申请日：2011-09-26
申请人： INTEL CORPORATION , CHEN, Huimin , ZHANG, Chunyu , DURLEY, Paul, S.
发明人： CHEN, Huimin , ZHANG, Chunyu , DURLEY, Paul, S.
IPC分类号： H04L29/10 , H04L29/06 , G06F13/14
摘要： Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

2. 发明申请

WO2013177777A1 AN ELECTRONIC INDICATOR DEVICE FOR CLEANING MONITORING 审中-公开
标题翻译：一种用于清洁监测的电子指示器装置
公开(公告)号：WO2013177777A1
公开(公告)日：2013-12-05
申请号：PCT/CN2012/076334
申请日：2012-05-31
申请人： 3M INNOVATIVE PROPERTIES COMPANY , ZHOU, Pingle , YANG, Yinghua , ZHANG, Chunyu , WEN, Zhiguo , LIU, Dong
发明人： ZHOU, Pingle , YANG, Yinghua , ZHANG, Chunyu , WEN, Zhiguo , LIU, Dong
IPC分类号： A61L2/24 , G01K13/02 , G01K1/02
CPC分类号： A61L2/26 , A61L2/04 , A61L2202/14 , A61L2202/26 , G01K1/02 , G01K3/04 , G01K13/02
摘要： An electronic indictor device (100) for cleaning monitoring can be disposed in a wash chamber of a washer-disinfector to monitor the efficacy of a cleaning cycle. The electronic indicator device (100) includes an environmental sensor (110) configured to generate signals indicative of environmental conditions and a processor (120) configured to determine the efficacy of the cleaning cycle based on the signals generated by the environmental sensor (110).
摘要翻译：用于清洁监测的电子指示装置（100）可以设置在洗衣机消毒器的洗涤室中，以监测清洁循环的功效。电子指示装置（100）包括被配置为产生指示环境条件的信号的环境传感器（110）和配置成基于由环境传感器（110）产生的信号来确定清洁循环的功效的处理器（120）。

3. 发明申请

WO2017112529A1 CONFIGURATION ARBITER FOR MULTIPLE CONTROLLERS SHARING A LINK INTERFACE 审中-公开
标题翻译：用于共享链路接口的多个控制器的配置仲裁器
公开(公告)号：WO2017112529A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/067046
申请日：2016-12-19
申请人： INTEL CORPORATION
发明人： CHELLAPPAN, Satheesh , ZHANG, Chunyu
IPC分类号： G06F13/36
CPC分类号： G06F13/37 , G06F1/12 , G06F1/26 , G06F13/4226
摘要： In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.
摘要翻译：在多个控制器共享链路接口但并非全部（1）与物理层的相同配置兼容或（2）使用相同时钟的系统中，配置仲裁子系统拦截，组织，并重新记录来自各种控制器代理的配置访问请求。优先级根据存储的策略进行分配。配置仲裁器授予对最高优先级代理的配置访问权限，将代理的消息与仲裁器的时钟同步。低优先级代理的消息存储在命令队列中，直到它们升至最高优先级。除了防止时序冲突和简化时钟协调之外，配置仲裁器还可以提供对控制器内置功能以外的物理层寄存器的访问，以进一步优化配置。

4. 发明申请

WO2017171967A1 MULTI-STANDARD SINGLE INTERFACE WITH REDUCED I/O COUNT 审中-公开
标题翻译：具有减少的I / O计数的多标准单接口
公开(公告)号：WO2017171967A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/013038
申请日：2017-01-11
申请人： INTEL CORPORATION
发明人： ZHANG, Chunyu , ARENDT, Kevin E. , SONG, Hongjiang
IPC分类号： G06F13/40
摘要： An apparatus is described having an electrical interface that supports a first specification and a second specification. The first specification specifies differentially transmitted data. The second specification specifies at least three transmitted data signals. The electrical interface includes a plurality of modular transmitter circuits where each transmitter circuit includes a single ended driver and a select circuit. The select circuit is to select either one end of a differential signal associated with the first specification or one of the at least three transmitted data signals associated with the second specification.
摘要翻译：描述了一种具有支持第一规范和第二规范的电接口的设备。第一个规范规定差分传输的数据。第二规范规定了至少三个传输的数据信号。电接口包括多个模块化发射器电路，其中每个发射器电路包括单端驱动器和选择电路。选择电路用于选择与第一规范相关的差分信号的一端或与第二规范相关的至少三个传输数据信号中的一个。

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