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1. 发明授权

US10230665B2 Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks 有权
公开(公告)号：US10230665B2
公开(公告)日：2019-03-12
申请号：US14136293
申请日：2013-12-20
申请人： INTEL CORPORATION
发明人： Thomas D. Lovett , Albert Cheng , Mark S. Birrittella , James Kunz , Todd Rimmer
IPC分类号： H04L12/933 , H04L12/911 , H04L1/00 , H04L12/851 , H04L12/805 , H04L12/863 , H04L12/865 , H04L1/12 , H04L25/14
摘要： Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.

2. 发明授权

US09385962B2 Method and system for flexible credit exchange within high performance fabrics 有权
标题翻译：高性能织物灵活信用交换的方法和系统
公开(公告)号：US09385962B2
公开(公告)日：2016-07-05
申请号：US14136605
申请日：2013-12-20
申请人： INTEL CORPORATION
发明人： Todd Rimmer , Thomas D. Lovett , Albert Cheng
IPC分类号： H04L12/801 , H04L12/919 , H04L12/925 , H04L12/933 , G06F13/42 , H04L12/931 , H04L12/861
CPC分类号： H04L47/39 , G06F5/065 , G06F13/1673 , G06F13/4221 , G06F2205/067 , H04L47/2408 , H04L47/2433 , H04L47/245 , H04L47/30 , H04L47/722 , H04L47/765 , H04L49/103 , H04L49/109 , H04L49/358 , H04L49/505 , H04L49/70 , H04L49/9057
摘要： Method, apparatus, and systems for implementing flexible credit exchange within high performance fabrics. Available buffer space in a receive buffer on a receive-side of a link is managed and tracked at the transmit-side of the link using credits. Peer link interfaces coupled via a link are provided with receive buffer configuration information that specifies how the receive buffer space in each peer is partitioned and space allocated for each buffer, including a plurality of virtual lane (VL) buffers. Credits are used for tracking buffer space consumption and in credits are returned from the receive-side indicating freed buffer space. The peer link interfaces exchange credit organization information to inform the other peer of how much space each credit represents. In connection with data transfer over the link, the transmit-side de-allocates credits based on an amount of buffer space to be consumed in applicable buffers in the receive buffer. Upon space being freed in the receive buffer, the receive-side returns credit ACKnowledgements (ACKs) identifying a VL for which space has been freed.
摘要翻译：在高性能织物中实现灵活信用交换的方法，设备和系统。在链路的接收侧的接收缓冲区中的可用缓冲区空间在链路的发送端使用信用进行管理和跟踪。通过链路耦合的对等链路接口提供有接收缓冲器配置信息，其指定如何对每个对等体中的接收缓冲区空间进行分区，并为每个缓冲区分配空间，包括多个虚拟通道（VL）缓冲区。积分用于跟踪缓冲区空间消耗，从接收端返回指示释放的缓冲区空间的信用。对等链接界面交换信用组织信息，通知对方每个信用代表多少空间。结合链路上的数据传输，发送侧基于在接收缓冲器中的适用缓冲器中消耗的缓冲区空间量去分配信用。在接收缓冲器中释放空间时，接收端返回识别已经释放空间的VL的信用确认（ACK）。

3. 发明授权

US09917787B2 Method and system for flexible credit exchange within high performance fabrics 有权
公开(公告)号：US09917787B2
公开(公告)日：2018-03-13
申请号：US15184375
申请日：2016-06-16
申请人： Intel Corporation
发明人： Todd Rimmer , Thomas D. Lovett , Albert Cheng
IPC分类号： H04L12/801 , H04L12/919 , H04L12/925 , H04L12/933 , H04L12/861 , G06F13/42 , H04L12/931 , H04L12/851 , G06F5/06 , G06F13/16
CPC分类号： H04L47/39 , G06F5/065 , G06F13/1673 , G06F13/4221 , G06F2205/067 , H04L47/2408 , H04L47/2433 , H04L47/245 , H04L47/30 , H04L47/722 , H04L47/765 , H04L49/103 , H04L49/109 , H04L49/358 , H04L49/505 , H04L49/70 , H04L49/9057
摘要： Method, apparatus, and systems for implementing flexible credit exchange within high performance fabrics. Available buffer space in a receive buffer on a receive-side of a link is managed and tracked at the transmit-side of the link using credits. Peer link interfaces coupled via a link are provided with receive buffer configuration information that specifies how the receive buffer space in each peer is partitioned and space allocated for each buffer, including a plurality of virtual lane (VL) buffers. Credits are used for tracking buffer space consumption and in credits are returned from the receive-side indicating freed buffer space. The peer link interfaces exchange credit organization information to inform the other peer of how much space each credit represents. In connection with data transfer over the link, the transmit-side de-allocates credits based on an amount of buffer space to be consumed in applicable buffers in the receive buffer. Upon space being freed in the receive buffer, the receive-side returns credit ACKnowledgements (ACKs) identifying a VL for which space has been freed.

4. 发明授权

US09648148B2 Method, apparatus, and system for QoS within high performance fabrics 有权
公开(公告)号：US09648148B2
公开(公告)日：2017-05-09
申请号：US14139930
申请日：2013-12-24
申请人： Intel Corporation
发明人： Todd Rimmer , Thomas D. Lovett , Albert Cheng
IPC分类号： H04L29/06 , H04L12/851 , H04L12/801 , H04L12/933 , H04L12/805 , H04L12/931
CPC分类号： H04L47/2425 , H04L47/2408 , H04L47/2458 , H04L47/2491 , H04L49/10 , H04L49/3045 , H04L49/358 , H04L49/70 , H04L69/22
摘要： Method, apparatus, and systems for implementing Quality of Service (QoS) within high performance fabrics. A multi-level QoS scheme is implemented including virtual fabrics, Traffic Classes, Service Levels (SLs), Service Channels (SCs) and Virtual Lanes (VLs). SLs are implemented for Layer 4 (Transport Layer) end-to-end transfer of fabric packets, while SCs are used to differentiate fabric packets at the Link Layer. Fabric packets are divided into flits, with fabric packet data transmitted via fabric links as flits streams. Fabric switch input ports and device receive ports detect SC IDs for received fabric packets and implement SC-to-VL mappings to determine VL buffers to buffer fabric packet flits in. An SL may have multiple SCs, and SC-to-SC mapping may be implemented to change the SC for a fabric packet as it is forwarded through the fabric, while maintaining its SL. A Traffic Class may include multiple SLs, enabling request and response traffic for an application to employ separate SLs.

5. 发明授权

US10469380B2 Table-driven routing in a dragonfly processor interconnect network 有权
公开(公告)号：US10469380B2
公开(公告)日：2019-11-05
申请号：US15063191
申请日：2016-03-07
申请人： Intel Corporation
发明人： Mike Parker , Steve Scott , Albert Cheng , Robert Alverson
IPC分类号： H04L12/741 , G06F15/173 , H04L12/701 , H04L12/729 , H04L12/751 , H04L12/713
摘要： A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables.

6. 发明申请

US20160294694A1 TABLE-DRIVEN ROUTING IN A DRAGONFLY PROCESSOR INTERCONNECT NETWORK 审中-公开
公开(公告)号：US20160294694A1
公开(公告)日：2016-10-06
申请号：US15063191
申请日：2016-03-07
申请人： Intel Corporation
发明人： Mike Parker , Steve Scott , Albert Cheng , Robert Alverson
IPC分类号： H04L12/741 , H04L12/713 , G06F15/173 , H04L12/729
CPC分类号： H04L45/745 , G06F15/17312 , G06F15/17362 , H04L45/00 , H04L45/02 , H04L45/10 , H04L45/125 , H04L45/586
摘要： A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables.

7. 发明申请

US20150208145A1 PROGRESSIVE ADAPTIVE ROUTING IN A DRAGONFLY PROCESSOR INTERCONNECT NETWORK 审中-公开
标题翻译：在连续处理器互连网络中进行自适应路由
公开(公告)号：US20150208145A1
公开(公告)日：2015-07-23
申请号：US14672125
申请日：2015-03-28
申请人： Intel Corporation
发明人： Mike Parker , Steve Scott , Albert Cheng , John Kim
IPC分类号： H04Q11/00 , H04B10/272
CPC分类号： H04L45/04 , H04B10/272 , H04L45/06 , H04L45/22 , H04L45/24 , H04L45/28 , H04Q11/0005
摘要： A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to adaptively route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more of network congestion information from neighboring routers and failed network link information from neighboring routers.
摘要翻译：多处理器计算机系统包括蜻蜓处理器互连网络，其包括多个处理器节点和多个路由器。基于来自相邻路由器的一个或多个网络拥塞信息和来自相邻路由器的故障网络链路信息，路由器可操作以通过从蜻蜓网络中的目标节点到目的地节点的多个网络路径中的选择来自适应地路由数据。

8. 发明申请

US20170237671A1 METHOD, APPARATUS, AND SYSTEM FOR QOS WITHIN HIGH PERFORMANCE FABRICS 审中-公开
公开(公告)号：US20170237671A1
公开(公告)日：2017-08-17
申请号：US15585366
申请日：2017-05-03
申请人： Intel Corporation
发明人： Todd Rimmer , Thomas D. Lovett , Albert Cheng
IPC分类号： H04L12/851 , H04L12/931 , H04L29/06
CPC分类号： H04L47/2425 , H04L47/2408 , H04L47/2458 , H04L47/2491 , H04L49/10 , H04L49/3045 , H04L49/358 , H04L49/70 , H04L69/22
摘要： Method, apparatus, and systems for implementing Quality of Service (QoS) within high performance fabrics. A multi-level QoS scheme is implemented including virtual fabrics, Traffic Classes, Service Levels (SLs), Service Channels (SCs) and Virtual Lanes (VLs). SLs are implemented for Layer 4 (Transport Layer) end-to-end transfer of fabric packets, while SCs are used to differentiate fabric packets at the Link Layer. Fabric packets are divided into flits, with fabric packet data transmitted via fabric links as flits streams. Fabric switch input ports and device receive ports detect SC IDs for received fabric packets and implement SC-to-VL mappings to determine VL buffers to buffer fabric packet flits in. An SL may have multiple SCs, and SC-to-SC mapping may be implemented to change the SC for a fabric packet as it is forwarded through the fabric, while maintaining its SL. A Traffic Class may include multiple SLs, enabling request and response traffic for an application to employ separate SLs.

9. 发明申请

US20150188817A1 TABLE-DRIVEN ROUTING IN A DRAGONFLY PROCESSOR INTERCONNECT NETWORK 审中-公开
标题翻译：在DRAGONFLY PROCESSOR INTERCONNECT NETWORK中的表驱动路由
公开(公告)号：US20150188817A1
公开(公告)日：2015-07-02
申请号：US14583579
申请日：2014-12-26
申请人： Intel Corporation
发明人： Mike Parker , Steve Scott , Albert Cheng , Robert Alverson
IPC分类号： H04L12/741 , H04L12/713 , H04L12/751
CPC分类号： H04L45/745 , G06F15/17312 , G06F15/17362 , H04L45/00 , H04L45/02 , H04L45/10 , H04L45/125 , H04L45/586
摘要： A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables.
摘要翻译：多处理器计算机系统包括蜻蜓处理器互连网络，其包括多个处理器节点和多个路由器。路由器可操作以基于一个或多个路由表从多个网络路径中的目标节点到蜻蜓网络中的目的节点进行选择来路由数据。

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