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1. 发明专利

JP2014160847A Germanium-based quantum well devices 有权
标题翻译：基于锗的量子阱器件
公开(公告)号：JP2014160847A
公开(公告)日：2014-09-04
申请号：JP2014081243
申请日：2014-04-10
申请人： Intel Corp , インテルコーポレイション
发明人： RAVI PILLARISETTY , JIN BEEN-YIH , CHU-KUNG BENJAMIN , MATTHEW V METZ , JACK T KAVALIEROS , MARKO RADOSAVLJEVIC , ROZA KOTLYAR , WILLY RACHMADY , NILOY MUKHERJEE , GILBERT DEWEY , CHAU ROBERT
IPC分类号： H01L29/812 , H01L21/336 , H01L21/338 , H01L21/8238 , H01L27/092 , H01L29/778 , H01L29/78
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： PROBLEM TO BE SOLVED: To provide germanium-based quantum well devices.SOLUTION: A quantum well transistor has a germanium quantum well channel region 208. A silicon-containing etch stop region 240 provides easy placement of a gate dielectric 216 close to the channel. A group III-V barrier region 206 adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译：要解决的问题：提供锗基量子阱器件。解决方案：量子阱晶体管具有锗量子阱沟道区域208.含硅蚀刻停止区域240提供了栅极电介质216容易放置在靠近沟道的位置。 III-V族阻挡区域206向通道增加应变。通道区域上方和下方的分级硅锗层提高性能。多栅极电介质材料允许使用高k值栅极电介质。

2. 发明专利

JP2013140999A Isolated tri-gate transistor fabricated on bulk substrate 有权
标题翻译：隔离三极晶体管在大块基板上制作
公开(公告)号：JP2013140999A
公开(公告)日：2013-07-18
申请号：JP2013025282
申请日：2013-02-13
申请人： Intel Corp , インテルコーポレイション
发明人： RAFAEL RIOS , JACK T KAVALIEROS , STEPHEN M CEA
IPC分类号： H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66795 , H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a tri-gate transistor process with improved short-channel effects.SOLUTION: A method comprises: patterning a bulk substrate to form a fin structure; depositing an insulating material around the fin structure; recessing the insulating material to expose a portion of the fin structure that will be used for the isolated tri-gate semiconductor body; depositing a nitride cap over the exposed portion of the fin structure, to protect the exposed portion of the fin structure; and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure located below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900°C and around 1100°C for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：要解决的问题：提供具有改善的短沟道效应的三栅极晶体管工艺。解决方案：一种方法包括：对大块基板进行构图以形成鳍结构; 在翅片结构周围沉积绝缘材料; 使绝缘材料凹陷以暴露将用于隔离三栅极半导体主体的鳍结构的一部分; 在所述翅片结构的暴露部分上沉积氮化物盖，以保护所述翅片结构的暴露部分; 并进行热氧化处理以氧化位于氮化物盖下方的翅片结构的未受保护部分。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时之间的时间。

3. 发明专利

GB2530194B Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon 未知
公开(公告)号：GB2530194B
公开(公告)日：2019-12-04
申请号：GB201520311
申请日：2013-06-28
申请人： INTEL CORP
发明人： NITI GOEL , RAVI PILLARISETTY , WILLY RACHMADY , JACK T KAVALIEROS , GILBERT DEWEY , BENJAMIN CHU-KUNG , MARKO RADOSAVLJEVIC , MATTHEW V METZ , NILOY MUKHERJEE , ROBERT S CHAU
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/267 , H01L29/66
摘要： Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

4. 发明专利

GB2529347B Making a defect free fin based device in lateral epitaxy overgrowth region 未知
公开(公告)号：GB2529347B
公开(公告)日：2019-04-17
申请号：GB201520613
申请日：2013-06-28
申请人： INTEL CORP
发明人： NITI GOEL , BENJAMIN CHU-KUNG , SANSAPTAK DASGUPTA , NILOY MUKHERJEE , MATTHEW V METZ , VAN H LE , JACK T KAVALIEROS , ROBERT S CHAU , RAVI PILLARISETTY
IPC分类号： H01L29/66
摘要： Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

5. 发明专利

GB2525332B Epitaxial film growth on patterned substrate 未知
公开(公告)号：GB2525332B
公开(公告)日：2017-09-06
申请号：GB201510570
申请日：2013-06-29
申请人： INTEL CORP
发明人： NITI GOEL , NILOY MUKHERJEE , SEUNG HOON SUNG , VAN H LE , MATTHEW V METZ , JACK T KAVALIEROS , RAVI PILLARISETTY , SANAZ K GARDNER , SANSAPTAK DASGUPTA , WILLY RACHMADY , BENJAMIN CHU-KUNG , MARKO RADOSAVLJEVIC , GILBERT DEWEY , MARC C FRENCH , JESSICA S KACHIAN , SURI SATYARTH , ROBERT S CHAU
IPC分类号： H01L21/20 , H01L21/02 , H01L21/762
摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.

6. 发明专利

GB2542975A EXPITAXIAL FILM ON NANOSCALE STRUCTURE 未知
公开(公告)号：GB2542975A
公开(公告)日：2017-04-05
申请号：GB201622139
申请日：2013-06-29
申请人： INTEL CORP
发明人： BENJAMIN CHU-KUNG , VAN H LE , ROBERT S CHAU , GILBERT DEWEY , NITIKA GOEL , JACK T KAVALIEROS , MATTHEW V METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY M ZELICK , SANSAPTAK DASGUPTA
IPC分类号： H01L29/423 , H01L29/775 , H01L29/786
摘要： An apparatus comprising: a substrate having a first lattice constant; an epitaxial (EPI) layer 315, having a second lattice constant different from the first lattice constant, including a bottom portion and opposing sidewall portions; and a transistor channel including the EPI layer; wherein the bottom portion includes a recess 316, wherein the recess is collinear with a long axis of a fin included in the apparatus. The EPI layer can act as a channel region of a gate all around transistor, where the recess can be filled with a gate dielectric and/or gate electrode material.

7. 发明专利

GB2542973A Expitaxial film on nanoscale structure 未知
公开(公告)号：GB2542973A
公开(公告)日：2017-04-05
申请号：GB201622126
申请日：2013-06-29
申请人： INTEL CORP
发明人： BENJAMIN CHU-KUNG , VAN H LE , ROBERT S CHAU , GILBERT DEWEY , NITIKA GOEL , JACK T KAVALIEROS , MATTHEW V METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY M ZELICK , SANSAPTAK DASGUPTA
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
摘要： An apparatus comprising: a fin structure having a first lattice constant and a top and opposing sidewall portions extending from the top towards a substrate; and an epitaxial (EPI) layer 115,116,117,118, having a second lattice constant different than the first lattice constant, formed on one of the top and sidewall portions; wherein the EPI layer comprises one of a group IV material and a group III-V material and the fin structure includes Si, wherein there is a buffer layer between the fin structure and the EPI layer, the buffer layer is less than 30 nm thick, and the EPI layer directly contacts the buffer layer.

8. 发明专利

BR112015029855A8 integrar estruturas de aleta compatíveis com vlsi com crescimento epitaxial seletivo e fabricar dispositivos nas mesmas 未知
公开(公告)号：BR112015029855A8
公开(公告)日：2019-12-24
申请号：BR112015029855
申请日：2013-06-28
申请人： INTEL CORP
发明人： BENJAMIN CHU-KUNG , GILBERT DEWEY , JACK T KAVALIEROS , MARKO RADOSAVLJEVIC , MATTHEW V METZ , NILOY MUKHERJEE , NITI GOEL , RAVI PILLARISETTY , ROBERT S CHAU , WILLY RACHMADY
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78
摘要： resumo "integrar estruturas de aleta compatíveis com vlsi com crescimento epitaxial seletivo e fabricar dispositivos nas mesmas" trata-se de diferentes tipos n e p de aletas de dispositivo que são formados por crescimento epitaxial das primeiras regiões epitaxiais de um material de primeiro tipo a partir de uma superfície de substrato em um fundo de primeiras trincheiras formadas entre regiões de isolamento de trincheira rasa (sti). as alturas das regiões de sti e da primeira trincheira são pelo menos 1,5 vez sua largura. as regiões de sti são removidas por corrosão para expor a superfície superior do substrato para formar as segundas trincheiras entre as primeiras regiões epitaxiais. uma camada de material espaçador é formada nas segundas trincheiras nas paredes laterais das primeiras regiões epitaxiais. faz-se com que as segundas regiões epitaxiais de um material de segundo tipo cresçam a partir da superfície de substrato em um fundo das segundas trincheiras entre as primeiras regiões epitaxiais. os pares de aletas do tipo n e p podem ser formados a partir da primeira e da segunda regiões epitaxiais. as aletas são cointegradas e têm defeitos reduzidos de incompatibilidade de retícula de interface de material.

9. 发明专利

GB2542975B EXPITAXIAL FILM ON NANOSCALE STRUCTURE 未知
公开(公告)号：GB2542975B
公开(公告)日：2017-10-11
申请号：GB201622139
申请日：2013-06-29
申请人： INTEL CORP
发明人： BENJAMIN CHU-KUNG , VAN H LE , ROBERT S CHAU , GILBERT DEWEY , NITIKA GOEL , JACK T KAVALIEROS , MATTHEW V METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY M ZELICK , SANSAPTAK DASGUPTA
IPC分类号： H01L29/423 , H01L29/775 , H01L29/786

10. 发明专利

GB2523931B Defect transferred and lattice mismatched epitaxial film 未知
公开(公告)号：GB2523931B
公开(公告)日：2017-09-06
申请号：GB201510571
申请日：2013-06-27
申请人： INTEL CORP
发明人： BENJAMIN CHU-KUNG , VAN H LE , ROBERT S CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK T KAVALIEROS , MATTHEW V METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY M ZELICK
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78
摘要： An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

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