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1. 发明公开

EP1623430A2 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SAME 审中-公开
标题翻译：半导体存储模块和方法用于其操作
公开(公告)号：EP1623430A2
公开(公告)日：2006-02-08
申请号：EP04760984.7
申请日：2004-05-11
申请人： Innovative Silicon, Inc. , Ecole Polytechnique Fédérale de Lausanne (EPFL)
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： G11C11/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

2. 发明申请

WO2004102576A3 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2004102576A3
公开(公告)日：2004-11-25
申请号：PCT/US2004/014691
申请日：2004-05-11
申请人： INNOVATIVE SILICON, INC. , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： G11C11/00
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

3. 发明公开

EP1623432A2 SEMICONDUCTOR MEMORY CELL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME 审中-公开
标题翻译：半导体存储单元阵列，建筑以及设备和操作方法THEREFOR的
公开(公告)号：EP1623432A2
公开(公告)日：2006-02-08
申请号：EP04751661.2
申请日：2004-05-07
申请人： Innovative Silicon, Inc. , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell (FIG. 3A, 3B) includes two transistors (102a, 102b) which store complementary data states (“0”, “1”). That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary '0') and the other transistor of the memory cell stores a logic high (a binary “l”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell (FIG. 4). That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

4. 发明申请

WO2004102625A2 SEMICONDUCTOR MEMORY CELLL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME 审中-公开
标题翻译：半导体存储器存储器，阵列，架构和器件及其操作方法
公开(公告)号：WO2004102625A2
公开(公告)日：2004-11-25
申请号：PCT/US2004/014363
申请日：2004-05-07
申请人： INNOVATIVE SILICON, INC. , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： H01L
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary "0") and the other transistor of the memory cell stores a logic high (a binary "ll"). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“ll”）。可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

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