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1. 发明专利

JP2011009769A Method of manufacturing semiconductor device and structure thereof 有权
标题翻译：制造半导体器件及其结构的方法
公开(公告)号：JP2011009769A
公开(公告)日：2011-01-13
申请号：JP2010184816
申请日：2010-08-20
申请人： Infineon Technologies Ag , インフィネオンテクノロジーズアクチエンゲゼルシャフト
发明人： GUTMANN ALOIS , NAUJOK MARKUS , PALLACHALIL MUHAMMED SHAFI KURIKKA VALAPPIL , WENDT HERMANN
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with reduced capacitance components by forming air gaps between the interconnects of integrated circuits.SOLUTION: A first insulating material is deposited on a substrate 202 and a second insulating material 232 having a sacrificial portion is deposited over the first insulating material. Conductive lines 210 are formed in first and second insulating layers by a damascene process. The second insulating material is treated for the removal of the first insulating material serving as the sacrificial portion, forming openings 238. Then, the first insulating material is removed to form air gaps 242 between the conductive lines. The second insulating material is impermeable when deposited, and is made permeable after being treated to remove the sacrificial portion through the second insulating material. The second insulating material is opened by etching or removed by annealing thermosensitive components.
摘要翻译：要解决的问题：提供一种通过在集成电路的互连之间形成气隙来制造具有减小的电容分量的半导体器件的方法。解决方案：第一绝缘材料沉积在衬底202上，第二绝缘材料232具有牺牲性部分沉积在第一绝缘材料上。导电线210通过镶嵌工艺形成在第一绝缘层和第二绝缘层中。处理第二绝缘材料以去除用作牺牲部分的第一绝缘材料，形成开口238.然后，去除第一绝缘材料，以在导线之间形成气隙242。第二绝缘材料在沉积时是不渗透的，并且在被处理以通过第二绝缘材料去除牺牲部分之后使其可渗透。通过蚀刻来打开第二绝缘材料，或通过退火热敏部件去除第二绝缘材料。

2. 发明专利

JP2006352124A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF 审中-公开
公开(公告)号：JP2006352124A
公开(公告)日：2006-12-28
申请号：JP2006163346
申请日：2006-06-13
申请人： INFINEON TECHNOLOGIES AG
发明人： GUTMANN ALOIS , NAUJOK MARKUS , PALLACHALIL MUHAMMED SHAFI KUR , WENDT HERMANN
IPC分类号： H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method that is improved to reduce the capacitive component C of the RC delay in an integrated circuit. SOLUTION: A first insulating material that becomes a sacrificial film is deposited on a substrate, and a second insulating material having a sacrificial portion is deposited on the first insulating material. The first insulating layer and the second insulating layer are patterned, and then a conductive material is vapor-deposited, and subsequently excess portions of the conductive material are removed, thereby forming conductive lines. In order to remove the sacrificial portion, pores or apertures are formed in the second insulating material for providing permeability. The first insulating material is removed through the pores or apertures, thereby forming air gaps between the conductive lines. After that, a cap layer is formed over the second insulating material and the conductive lines. As a result, air gaps are formed between the conductive lines. COPYRIGHT: (C)2007,JPO&INPIT

3. 发明申请

WO2006103158A3 INTEGRATION SCHEME FOR FULLY SILICIDED GATE 审中-公开
标题翻译：完全硅化门的集成方案
公开(公告)号：WO2006103158A3
公开(公告)日：2006-12-07
申请号：PCT/EP2006060632
申请日：2006-03-10
申请人： INFINEON TECHNOLOGIES AG , CULMSEE MARCUS , DONI LOTHAR , WENDT HERMANN
发明人： CULMSEE MARCUS , DONI LOTHAR , WENDT HERMANN
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/665 , H01L21/28097 , H01L29/66545 , H01L29/6656
摘要： To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such, as an oxide sidewall spacer and a nitride sidewall spacer, is formed adjacent the sidewall of the gate structure. The semiconductor body is then doped to form a source region and a drain region that are self-aligned to the spacers. The sacrificial layer can then be removed selectively with respect to the oxide sidewall spacer, the nitride sidewall spacer and the silicon gate. A metal layer (e.g., nickel) is formed over the source region, the drain region and the silicon gate and reacted with these regions to form a suicided source contact, a suicided drain contact and a suicided gate.
摘要翻译：为了形成半导体器件，在栅极电介质上方形成硅（例如多晶硅）栅极层，并且在硅栅极层上方形成牺牲层（优选氮化钛）。硅栅极层和牺牲层被图案化以形成栅极结构。间隔物，例如氧化物侧壁间隔物和氮化物侧壁间隔物，形成在栅极结构的侧壁附近。然后对半导体本体进行掺杂以形成与隔离物自对准的源极区和漏极区。然后可相对于氧化物侧壁间隔物，氮化物侧壁间隔物和硅栅极选择性地去除牺牲层。在源极区域，漏极区域和硅栅极上方形成金属层（例如，镍），并与这些区域反应以形成硅化源极接触，硅化漏极接触和硅化栅极。

4. 发明申请

WO0036636A3 CAPACITOR ELECTRODE 审中-公开
标题翻译：电容电极
公开(公告)号：WO0036636A3
公开(公告)日：2000-08-10
申请号：PCT/DE9903926
申请日：1999-12-08
申请人： INFINEON TECHNOLOGIES AG , WENDT HERMANN , BEITEL GERHARD , REISINGER HANS
发明人： WENDT HERMANN , BEITEL GERHARD , REISINGER HANS
IPC分类号： H01L21/02 , H01L21/285 , H01L21/8242
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： The aim of the invention is to create a microelectronic structure which prevents oxidation of oxygen-sensitive structures (25). To this end, the microelectronic structure is provided with a conductive layer (10) consisting of a platinum iridium alloy. The iridium should hamper the oxygen diffusion through the conductive layer (10) by binding the oxygen when the microelectronic structure is treated in a oxygen-containing atmosphere. Oxidation-sensitive structures (25) are thus protected underneath the conductive layer (10).
摘要翻译：它是要创建的微电子结构，其防止对氧敏感的结构（25）的氧化。为了这个目的，在微电子结构的导电层（10）由铂铱合金制成。铱应通过结合氧气阻碍通过导电层（10）中的氧扩散，从而保护用一种处理微电子结构的导电层（10）下方的氧化敏感的结构（25）在含氧气氛。

5. 发明专利

DE102016206596A1 Magnetoresistive Vorrichtungen und Verfahren zur Herstellung magnetoresistiver Vorrichtungen 未知
公开(公告)号：DE102016206596A1
公开(公告)日：2016-11-24
申请号：DE102016206596
申请日：2016-04-19
申请人： INFINEON TECHNOLOGIES AG
发明人： PRUEGL KLEMENS , RABERG WOLFGANG , STRASSER ANDREAS , WENDT HERMANN
IPC分类号： H01L43/12 , G01R33/09 , H01L21/321 , H01L43/08
摘要： Eine magnetoresistive Vorrichtung kann einen magnetoresistiven Stapel und eine Ätzstoppschicht ESL umfassen, die auf dem magnetoresistiven Stapel angeordnet ist. Ein Verfahren zur Herstellung der magnetoresistiven Vorrichtung kann Folgendes umfassen: Abscheiden des magnetoresistiven Stapels, der ESL und einer Maskenschicht auf einem Substrat; Vornehmen eines ersten Ätzprozesses, um einen Abschnitt der Maskenschicht zu ätzen, um einen Abschnitt der ESL freizulegen; und Vornehmen eines zweiten Ätzprozesses, um den freiliegenden Abschnitt der ESL und einen Abschnitt des magnetoresistiven Stapels zu ätzen. Das Verfahren kann ferner umfassen: Abscheiden einer Photoresistschicht auf der Hartmaske vor dem ersten Ätzprozess und Entfernen der Photoresistschicht von der Hartmaske nach dem ersten Ätzprozess. Der erste und zweite Ätzprozess können verschieden sein. Beispielsweise kann der erste Ätzprozess ein reaktiver Ätzprozess sein, und der zweite Ätzprozess kann ein nicht-reaktiver Ätzprozess sein.

6. 发明专利

DE102009000625A1 未知
公开(公告)号：DE102009000625A1
公开(公告)日：2009-10-01
申请号：DE102009000625
申请日：2009-02-04
申请人： INFINEON TECHNOLOGIES AG
发明人： KALTALIOGLU ERDEM , RIESS PHILIPP , WENDT HERMANN
IPC分类号： H01L21/768 , H01L21/311 , H01L21/3205 , H01L23/52
摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

7. 发明专利

DE59913465D1 未知
公开(公告)号：DE59913465D1
公开(公告)日：2006-06-29
申请号：DE59913465
申请日：1999-07-05
申请人： INFINEON TECHNOLOGIES AG
发明人： HANEDER PETER , REISINGER HANS , STENGL REINHARD , BACHHOFER HARALD , WENDT HERMANN , HOENLEIN WOLFGANG
IPC分类号： H01L21/8247 , H01L29/786 , G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792
摘要： A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

8. 发明专利

DE59704768D1 未知
公开(公告)号：DE59704768D1
公开(公告)日：2001-11-08
申请号：DE59704768
申请日：1997-06-24
申请人： INFINEON TECHNOLOGIES AG
发明人： SCHAEFER HERBERT , FRANOSCH MARTIN , STENGL REINHARD , LEHMANN VOLKER , REISINGER HANS , WENDT HERMANN
IPC分类号： C23C16/04 , H01L21/033 , H01L21/20 , H01L21/205 , H01L21/266 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/3205 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L27/11517 , H01L29/788 , H01L29/792
摘要： The mfg. method provides a fine structure at the surface of a substrate (1,2,3) using a cathodic vapour deposition process, effected with a process gas containing SiH4 and GeH4 in a carrier gas, for providing raised areas (4) determining the size of the fine structures. The raised areas act as a mask for an etching or implantation process and have a mean dia. and mean spacing of the order of between 1 and 100nm.

9. 发明专利

DE102011055224B4 Verfahren zum Herstellen eines Halbleiterchips und ein Halbleiterchip 未知
公开(公告)号：DE102011055224B4
公开(公告)日：2018-09-27
申请号：DE102011055224
申请日：2011-11-10
申请人： INFINEON TECHNOLOGIES AG
发明人： MENATH MARKUS , WENDT HERMANN , SCHUDERER BERTHOLD
IPC分类号： H01L21/78 , H01L21/304 , H01L21/306 , H01L29/06
摘要： Verfahren zum Herstellen eines Halbleiterchips (22, 32, 40), wobei das Verfahren Folgendes umfasst:Strukturieren eines Halbleiter-Substrats (20, 30), um mehrere Halbleiterchips (22, 32, 40) herzustellen, so dass jeder Halbleiterchip eine erste Hauptfläche (22A, 32A, 40A), mehrere Seitenflächen (22B, 32B, 40C) und eine zweite Hauptfläche (40B) gegenüber der ersten Hauptfläche umfasst;Ausbilden einer Einkerbung (22C, 32C, 40D) an einem Übergang zwischen der ersten Hauptfläche und den Seitenflächen jedes Halbleiterchips; undAbscheiden einer Metallschicht auf der zweiten Hauptfläche und den Seitenflächen.

10. 发明专利

DE59914245D1 未知
公开(公告)号：DE59914245D1
公开(公告)日：2007-04-19
申请号：DE59914245
申请日：1999-05-12
申请人： INFINEON TECHNOLOGIES AG
发明人： REISINGER HANS , LEHMANN VOLKER , STENGL REINHARD , WENDT HERMANN , LANGE GERRIT , BACHHOFER HARALD , FRANOSCH MARTIN , SCHAEFER HERBERT
IPC分类号： H01L21/8242 , H01L27/108
摘要： A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

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