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1. 发明申请

US20130012023A1 METHOD OF FORMING MICROPATTERN, METHOD OF FORMING DAMASCENE METALLIZATION, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED USING THE SAME 有权
标题翻译：形成微孔板的方法，形成金刚石金属化的方法以及使用其制造的半导体器件和半导体存储器件
公开(公告)号：US20130012023A1
公开(公告)日：2013-01-10
申请号：US13533653
申请日：2012-06-26
申请人： In-sun Park , Gil-heyun Choi , Ji-soon Park , Jong-myeong Lee , Jong-won Hong , Hei-seung Kim
发明人： In-sun Park , Gil-heyun Choi , Ji-soon Park , Jong-myeong Lee , Jong-won Hong , Hei-seung Kim
IPC分类号： H01L21/308
CPC分类号： H01L23/48 , H01L21/0337 , H01L21/31144 , H01L21/3212 , H01L21/76816 , H01L23/522 , H01L27/11565 , H01L27/1157 , H01L29/06 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.
摘要翻译：根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。

2. 发明授权

US08709937B2 Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same 有权
标题翻译：形成微图案的方法，形成镶嵌金属化的方法，以及使用其形成的半导体器件和半导体存储器件
公开(公告)号：US08709937B2
公开(公告)日：2014-04-29
申请号：US13533653
申请日：2012-06-26
申请人： In-sun Park , Gil-heyun Choi , Ji-soon Park , Jong-myeong Lee , Jong-won Hong , Hei-seung Kim
发明人： In-sun Park , Gil-heyun Choi , Ji-soon Park , Jong-myeong Lee , Jong-won Hong , Hei-seung Kim
IPC分类号： H01L21/4763
CPC分类号： H01L23/48 , H01L21/0337 , H01L21/31144 , H01L21/3212 , H01L21/76816 , H01L23/522 , H01L27/11565 , H01L27/1157 , H01L29/06 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.
摘要翻译：根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。

3. 发明授权

US09355851B2 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09355851B2
公开(公告)日：2016-05-31
申请号：US13588393
申请日：2012-08-17
申请人： Jong-Won Hong , Hei-Seung Kim , Kyoung-hee Nam , In-sun Park , Jong-Myeong Lee
发明人： Jong-Won Hong , Hei-Seung Kim , Kyoung-hee Nam , In-sun Park , Jong-Myeong Lee
IPC分类号： H01L21/762 , H01L21/763 , H01L21/288 , H01L23/532 , H01L27/115 , H01L21/768 , H01L27/108
CPC分类号： H01L21/76879 , H01L21/2885 , H01L21/76846 , H01L21/76847 , H01L21/76861 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L21/76882 , H01L23/53238 , H01L27/10894 , H01L27/10897 , H01L27/11529 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.
摘要翻译：半导体器件包括填充通过衬底上的绝缘中间层的至少一部分形成并包括铜的沟槽的金属图案，以及金属图案中的包含钽，氮化钽，钛，钛中的至少一种的润湿改善层图案氮化物，钌，钴和锰。

4. 发明授权

US06964922B2 Methods for forming metal interconnections for semiconductor devices having multiple metal depositions 有权
标题翻译：用于形成具有多个金属沉积的半导体器件的金属互连的方法
公开(公告)号：US06964922B2
公开(公告)日：2005-11-15
申请号：US10353386
申请日：2003-01-28
申请人： Jong-myeong Lee , Hyeon-deok Lee , In-sun Park , Ju-bum Lee
发明人： Jong-myeong Lee , Hyeon-deok Lee , In-sun Park , Ju-bum Lee
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76855 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L21/76882 , H01L2221/1089
摘要： Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.
摘要翻译：形成集成电路器件的方法可以包括在包括其导电部分的集成电路衬底上形成层间电介质膜。所述层间电介质膜包括露出所述集成电路基板的所述导电部分的一部分的接触孔，并且所述电介质膜包括与所述接触孔连通的沟槽，其中所述沟槽位于所述层间绝缘膜的与所述集成电路基板相对的表面中电路基板。相对于与集成电路基板相对的层间电介质膜的表面，优选在接触孔中形成第一金属层以形成第一金属层。在接触孔中优先形成第一金属层之后，在与集成电路基板相对的层间绝缘膜的表面上形成第二金属层。

5. 发明申请

US20070074522A1 Cryogenic refrigerator including separating device 审中-公开
标题翻译：低温冰箱包括分离装置
公开(公告)号：US20070074522A1
公开(公告)日：2007-04-05
申请号：US11512345
申请日：2006-08-30
申请人： Choon-dong Kim , Hyun-man Jang , In-sun Park , Ig-saeng Kim , Do-hyung Kim
发明人： Choon-dong Kim , Hyun-man Jang , In-sun Park , Ig-saeng Kim , Do-hyung Kim
IPC分类号： F25B9/00
CPC分类号： F25B9/14 , F25B2309/001
摘要： A cryogenic refrigerator has a separating device provided between a lower temperature portion and a heat exchanger to selectively separate the lower temperature portion and the heat exchanger, and thus to selectively block heat transfer between the lower temperature portion and the heat exchanger. According to the cryogenic refrigerator, it can have an ability to perform a maintenance operation of the cryogenic refrigerator at normal temperature by blocking heat transfer from the lower temperature portion to the heat exchanger during maintenance after disassembly.
摘要翻译：低温冷冻机具有设置在下部温度部和热交换器之间的分离装置，以选择性地分离下部温度部和热交换器，从而选择性地阻止下部温度部和热交换器之间的热传递。根据低温冰箱，能够通过在拆卸后的维护期间阻止从低温部向热交换器的热传递而在常温下进行低温冷冻机的维护操作。

6. 发明授权

US5879982A Methods of forming integrated circuit memory devices having improved electrical interconnects therein 失效
标题翻译：形成其中具有改进的电互连的集成电路存储器件的方法
公开(公告)号：US5879982A
公开(公告)日：1999-03-09
申请号：US948566
申请日：1997-10-10
申请人： In-sun Park , Byung-hee Kim , Se-jun Oh , Sang-min Lee
发明人： In-sun Park , Byung-hee Kim , Se-jun Oh , Sang-min Lee
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8239 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10844 , H01L27/1052 , H01L27/10852
摘要： Methods of forming integrated circuit memory devices include the steps of forming a first electrically insulating layer on a semiconductor substrate containing memory cells in a memory cell array region and peripheral circuits for driving the memory cells in a peripheral circuit region adjacent the memory cell array region. An etch-stopping layer is then formed on the first electrically insulating layer and then steps are performed to form a first electrically conductive layer on the etch-stopping layer, form a ferroelectric layer on the first electrically conductive layer, form a second electrode layer on the ferroelectric layer, etch the second electrode layer and ferroelectric layer in sequence using a first mask to define a second electrode and then etch the first electrically conductive layer using a second mask to simultaneously define a first electrode and a first interconnection layer comprising the same material. A second electrically insulating layer is then formed on the second electrode and first interconnection layer. First and second vias are then formed in the second electrically insulating layer, to expose the second electrode and first interconnection layer, respectively. A second electrically conductive layer is then patterned in the first and second vias.
摘要翻译：形成集成电路存储器件的方法包括以下步骤：在包含存储单元阵列区域中的存储单元的半导体衬底上形成第一电绝缘层，以及用于驱动与存储单元阵列区域相邻的外围电路区域中的存储单元的外围电路。然后在第一电绝缘层上形成蚀刻停止层，然后执行步骤以在蚀刻停止层上形成第一导电层，在第一导电层上形成铁电层，形成第二电极层铁电层，使用第一掩模依次蚀刻第二电极层和铁电层以限定第二电极，然后使用第二掩模蚀刻第一导电层，以同时限定第一电极和包含相同材料的第一互连层。然后在第二电极和第一互连层上形成第二电绝缘层。然后在第二电绝缘层中形成第一和第二通孔，以分别露出第二电极和第一互连层。然后在第一和第二通孔中将第二导电层图案化。

7. 发明授权

US06747354B2 Semiconductor devices having multilevel interconnections and methods for manufacturing the same 有权
标题翻译：具有多层互连的半导体器件及其制造方法
公开(公告)号：US06747354B2
公开(公告)日：2004-06-08
申请号：US10370222
申请日：2003-02-19
申请人： Hyun-young Kim , In-sun Park , Hyeon-deok Lee
发明人： Hyun-young Kim , In-sun Park , Hyeon-deok Lee
IPC分类号： H01L2348
CPC分类号： H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metal interconnection layer on a semiconductor substrate, an intermetal dielectric layer on the first metal interconnection layer and a second metal interconnection layer formed on the intermetal dielectric layer. A contact stud electrically connects the first and second metal interconnection layers through the intermetal dielectric layer, and includes a titanium/aluminum (TiAlx) core extending from the first metal interconnection layer toward the second metal interconnection layer. In method embodiments, a portion of an insulating layer of a semiconductor substrate is removed to form a hole that exposes an underlying conductive layer. A glue layer, e.g., a titanium (Ti) layer, is formed on bottom and sidewalls of the hole. A Ti seed layer is formed on the glue layer in the hole. An aluminum-containing layer is formed on the Ti seed layer. The substrate is thermally treated to form a contact stud including a TiAlx core.
摘要翻译：半导体器件包括在半导体衬底上的第一金属互连层，第一金属互连层上的金属间电介质层和形成在金属间电介质层上的第二金属互连层。接触柱将第一和第二金属互连层通过金属间电介质层电连接，并且包括从第一金属互连层向第二金属互连层延伸的钛/铝（TiAlx）芯。在方法实施例中，去除半导体衬底的绝缘层的一部分以形成暴露下面的导电层的孔。在孔的底部和侧壁上形成胶层，例如钛（Ti）层。在孔中的胶层上形成Ti种子层。在Ti种子层上形成含铝层。将基底热处理以形成包括TiAlx芯的接触柱。

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