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    • 4. 发明申请
    • Simulation System with Guided Backtracking
    • 引导回溯仿真系统
    • US20080126063A1
    • 2008-05-29
    • US11534238
    • 2006-09-22
    • Ilan BeerEyal BinDaniel GeistZiv NevoGil Eliezer ShurekAvi Ziv
    • Ilan BeerEyal BinDaniel GeistZiv NevoGil Eliezer ShurekAvi Ziv
    • G06F17/50
    • G06F17/5022
    • A method for design verification includes running a simulation of a design in a simulation environment, which comprises a stimuli generator for providing inputs to the design during the simulation. Respective measures of quality are computed for at least some of the simulation states in a sequence of states generated by the environment. State data are saved with respect to at least one of the simulation states. The state data include indications both of the respective simulated state and of the respective environment state. Responsively to the respective measures of quality, the saved state data are recalled so as to restart the simulation from the at least one of the simulation states by returning the design to the respective simulated state and returning the simulation environment to the respective environment state.
    • 一种用于设计验证的方法包括在仿真环境中运行设计的仿真,其包括在仿真期间向设计提供输入的刺激发生器。 对由环境生成的状态序列中的至少一些模拟状态计算质量的相关度量。 关于至少一个模拟状态来保存状态数据。 状态数据包括各自的模拟状态和各个环境状态的指示。 响应于各种质量测量,通过将设计返回到相应的模拟状态并将模拟环境返回到各自的环境状态,调用保存的状态数据以便从至少一个模拟状态重新启动模拟。
    • 7. 发明授权
    • Simulation monitors based on temporal formulas
    • 基于时间公式的仿真显示器
    • US07188061B2
    • 2007-03-06
    • US10196702
    • 2002-07-15
    • Ilan BeerSharon Keidar
    • Ilan BeerSharon Keidar
    • G06F9/45
    • G06F17/504
    • A method for design verification includes receiving a software model of a design of a system under evaluation, and providing a property, which is dependent on a specified variable having a predefined range of values. The property applies to all states of the system for any selected value among the values of the variable within the predefined range. The property is processed so as to generate a checker program for detecting a violation of the property. A simulation of the system is then run using the software model together with the checker program.
    • 一种用于设计验证的方法包括接收正在评估的系统的设计的软件模型,并且提供依赖于具有预定范围值的指定变量的属性。 该属性适用于系统的所有状态,用于在预定范围内的变量值中的任何所选值。 该属性被处理以产生用于检测违反该属性的检查程序。 然后使用软件模型与检查程序一起运行系统的仿真。
    • 8. 发明授权
    • Method and system for reducing state space variables prior to symbolic model checking
    • 在符号模型检查之前减少状态空间变量的方法和系统
    • US06192505B1
    • 2001-02-20
    • US09124360
    • 1998-07-29
    • Ilan BeerCindy EisnerYoav Rodeh
    • Ilan BeerCindy EisnerYoav Rodeh
    • G06F1750
    • G06F17/504
    • A computer-implemented method for systematically eliminating redundant circuit elements in a state machine of a model having sequential circuit elements possessing one of a fixed number of possible states, typically “0” and “1”. Initially, the sequential circuit elements are sorted into groups whose state is determinate i.e. equal to “0” or “1”. The state of each circuit element whose state is determinate is stored in memory and its next state is calculated and compared with its preceding state. Each circuit element whose successive states are different is moved to the group of indeterminate circuit elements, and the cycle is repeated in respect of all remaining determinate circuit elements until no further circuit elements are moved. Each of the remaining determinate circuit elements is then replaced by a constant equal to its corresponding state i.e. “0” or “1”. Finally, any circuit elements whose output is connected to one or more of the replaced circuit elements and to no other circuit elements is eliminated from the model.
    • 一种用于系统地消除模型的状态机中的冗余电路元件的计算机实现的方法,其具有具有固定数量的可能状态(通常为“0”和“1”)之一的顺序电路元件。 最初,顺序电路元件被分类为其状态确定为等于“0”或“1”的组。 其状态确定的每个电路元件的状态被存储在存储器中,并且其下一个状态被计算并与之前的状态进行比较。 其连续状态不同的每个电路元件被移动到不确定电路元件组,并且相对于所有剩余的确定电路元件重复该循环,直到不再有电路元件移动。 然后将剩余的确定电路元件中的每一个替换为等于其对应状态即“0”或“1”的常数。 最后,从模型中消除了输出连接到一个或多个替代的电路元件和没有其它电路元件的任何电路元件。