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    • 2. 发明申请
    • GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE GATE DRIVING CIRCUIT
    • 门驱动电路和具有门驱动电路的显示装置
    • US20100164915A1
    • 2010-07-01
    • US12539095
    • 2009-08-11
    • Hak-Gyu KimYoung-Joo ParkJi-Suk Lim
    • Hak-Gyu KimYoung-Joo ParkJi-Suk Lim
    • G06F3/038H03K3/00
    • G09G3/3677H03K19/00361
    • A gate driving circuit includes a first shift register and a second shift register for driving odd gate lines. The first shift register includes a first plurality of cascade-connected stages that sequentially output a plurality of first gate signals. A first stage of the first shift register receives a first vertical start signal. The second shift register includes a second plurality of cascade-connected stages to sequentially output a plurality of second gate signals. The first stage of the second shift register receives an output signal of the first stage of the first shift register as its vertical start signal. A data charging rate may be improved by ensuring the timing margin of each gate signal, so that the driving reliability of the gate driving circuit may be improved.
    • 栅极驱动电路包括用于驱动奇数栅极线的第一移位寄存器和第二移位寄存器。 第一移位寄存器包括顺序地输出多个第一栅极信号的第一多个级联连接级。 第一移位寄存器的第一级接收第一垂直起始信号。 第二移位寄存器包括第二多个级联连接的级,以顺序地输出多个第二门信号。 第二移位寄存器的第一级接收第一移位寄存器的第一级的输出信号作为其垂直起始信号。 可以通过确保每个栅极信号的定时裕度来提高数据充电速率,从而可以提高栅极驱动电路的驱动可靠性。
    • 3. 发明授权
    • Gate driving circuit and display device having the gate driving circuit
    • 栅极驱动电路和具有栅极驱动电路的显示装置
    • US08654055B2
    • 2014-02-18
    • US12539095
    • 2009-08-11
    • Hak-Gyu KimYoung-Joo ParkJi-Suk Lim
    • Hak-Gyu KimYoung-Joo ParkJi-Suk Lim
    • G09G3/36
    • G09G3/3677H03K19/00361
    • A gate driving circuit includes a first shift register and a second shift register for driving odd gate lines. The first shift register includes a first plurality of cascade-connected stages that sequentially output a plurality of first gate signals. A first stage of the first shift register receives a first vertical start signal. The second shift register includes a second plurality of cascade-connected stages to sequentially output a plurality of second gate signals. The first stage of the second shift register receives an output signal of the first stage of the first shift register as its vertical start signal. A data charging rate may be improved by ensuring the timing margin of each gate signal, so that the driving reliability of the gate driving circuit may be improved.
    • 栅极驱动电路包括用于驱动奇数栅极线的第一移位寄存器和第二移位寄存器。 第一移位寄存器包括顺序地输出多个第一栅极信号的第一多个级联连接级。 第一移位寄存器的第一级接收第一垂直起始信号。 第二移位寄存器包括第二多个级联连接的级,以顺序地输出多个第二门信号。 第二移位寄存器的第一级接收第一移位寄存器的第一级的输出信号作为其垂直起始信号。 可以通过确保每个栅极信号的定时裕度来提高数据充电速率,从而可以提高栅极驱动电路的驱动可靠性。