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1. 发明授权

US07924588B2 Content addressable memory with concurrent two-dimensional search capability in both row and column directions 有权
标题翻译：内容可寻址存储器，具有行和列方向的并行二维搜索功能
公开(公告)号：US07924588B2
公开(公告)日：2011-04-12
申请号：US11949065
申请日：2007-12-03
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

2. 发明授权

US08233302B2 Content addressable memory with concurrent read and search/compare operations at the same memory cell 有权
标题翻译：内容可寻址存储器，在同一个存储单元中具有并发读取和搜索/比较操作
公开(公告)号：US08233302B2
公开(公告)日：2012-07-31
申请号：US12983995
申请日：2011-01-04
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

3. 发明申请

US20110096582A1 CONTENT ADDRESSABLE MEMORY WITH CONCURRENT TWO-DIMENSIONAL SEARCH CAPABILITY IN BOTH ROW AND COLUMN DIRECTIONS 有权
标题翻译：内容可寻址的存储器，具有两个二维搜索能力，在两个方向和列方向
公开(公告)号：US20110096582A1
公开(公告)日：2011-04-28
申请号：US12983995
申请日：2011-01-04
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

4. 发明申请

US20090141528A1 APPARATUS AND METHOD FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY 有权
标题翻译：实现增强内容可寻址记忆性能能力的装置和方法
公开(公告)号：US20090141528A1
公开(公告)日：2009-06-04
申请号：US11949065
申请日：2007-12-03
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

5. 发明申请

US20090141530A1 STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY 审中-公开
标题翻译：实现增强内容可寻址记忆性能能力的结构
公开(公告)号：US20090141530A1
公开(公告)日：2009-06-04
申请号：US12110582
申请日：2008-04-28
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wisort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wisort
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括具有以行和列排列的存储单元阵列的内容寻址存储器（CAM）设备; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

6. 发明授权

US07940581B2 Method for low power sensing in a multi-port SRAM using pre-discharged bit lines 有权
标题翻译：使用预放电位线的多端口SRAM中的低功率感测方法
公开(公告)号：US07940581B2
公开(公告)日：2011-05-10
申请号：US12861026
申请日：2010-08-23
申请人： Igor Arsovski , Michael T. Fragano , Robert M. Houle
发明人： Igor Arsovski , Michael T. Fragano , Robert M. Houle
IPC分类号： G11C7/06
CPC分类号： G11C8/16 , G11C11/419
摘要： A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.
摘要翻译：一种用于感测静态随机存取存储器（SRAM）内的存储单元的内容的方法包括当存储单元未被访问时，将与存储单元相关联的位线保持在零电压电位; 在存储器单元的访问期间将位线激励到不同于零电压电位的第一电压电位; 以及当相关联的位线已经达到第一电压电位时感测存储器单元的内容。

7. 发明授权

US07986571B2 Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines 有权
标题翻译：使用预放电位线的多端口SRAM中的低功耗，单端感测
公开(公告)号：US07986571B2
公开(公告)日：2011-07-26
申请号：US12858499
申请日：2010-08-18
申请人： Igor Arsovski , Michael T. Fragano , Robert M. Houle
发明人： Igor Arsovski , Michael T. Fragano , Robert M. Houle
IPC分类号： G11C7/06
CPC分类号： G11C7/12 , G11C11/412 , G11C11/413
摘要： An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.
摘要翻译：在使用预放电位线的多端口静态随机存取存储器（SRAM）中用于低功率，单端感测的装置和方法包括：当存储器单元为存储单元时，将与存储器单元相关联的位线保持在零电压电位没有被访问当存储器单元被访问时，释放位线保持在零电压电位; 在存储单元访问期间将位线充电到比零电压电位大的第一电压电位，其中在访问存储器单元之后第一预定时间段内的位线充电到第一电压电位，开始了以及在所述存储器单元的访问期间感测所述存储器单元的内容，其中在开始访问所述存储器单元之后的第二预定时间段内存储单元内容的感测发生。

8. 发明申请

US20090129181A1 SYSTEM AND METHOD FOR IMPLEMENTING ROW REDUNDANCY WITH REDUCED ACCESS TIME AND REDUCED DEVICE AREA 有权
标题翻译：用于实现减少访问时间和减少设备区域的冗余的系统和方法
公开(公告)号：US20090129181A1
公开(公告)日：2009-05-21
申请号：US11941994
申请日：2007-11-19
申请人： Michael T. Fragano , Harold Pilo
发明人： Michael T. Fragano , Harold Pilo
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C29/844
摘要： A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.
摘要翻译：用于在集成电路存储器件中实现行冗余的系统包括具有字线，位线和存储单元器件的一个或多个主子阵列，所述一个或多个主子阵列中的每一个包括与其相关联的一组支持电路。离散的冗余子阵列与主子阵列相关联，并且还包括与其相关联的一组支持电路。一个共同的全局位线由主子阵列和冗余子阵列共享，并且冗余转向控制电路与主子阵列和冗余子阵列相关联。冗余转向控制电路被配置为使得与冗余转向控制电路执行的地址比较操作并行执行主子阵列和冗余子阵列的字线激活。

9. 发明授权

US07609569B2 System and method for implementing row redundancy with reduced access time and reduced device area 有权
标题翻译：实现行冗余的系统和方法，减少了访问时间，减少了设备面积
公开(公告)号：US07609569B2
公开(公告)日：2009-10-27
申请号：US11941994
申请日：2007-11-19
申请人： Michael T. Fragano , Harold Pilo
发明人： Michael T. Fragano , Harold Pilo
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C29/844
摘要： A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.
摘要翻译：用于在集成电路存储器件中实现行冗余的系统包括具有字线，位线和存储单元器件的一个或多个主子阵列，所述一个或多个主子阵列中的每一个包括与其相关联的一组支持电路。离散的冗余子阵列与主子阵列相关联，并且还包括与其相关联的一组支持电路。一个共同的全局位线由主子阵列和冗余子阵列共享，并且冗余转向控制电路与主子阵列和冗余子阵列相关联。冗余转向控制电路被配置为使得与冗余转向控制电路执行的地址比较操作并行执行主子阵列和冗余子阵列的字线激活。

10. 发明授权

US06944075B1 Variable column redundancy region boundaries in SRAM 失效
标题翻译： SRAM中的可变列冗余区域边界
公开(公告)号：US06944075B1
公开(公告)日：2005-09-13
申请号：US10905451
申请日：2005-01-05
申请人： Steven M. Eustis , Michael T. Fragano , Michael R. Ouellette
发明人： Steven M. Eustis , Michael T. Fragano , Michael R. Ouellette
IPC分类号： G11C7/00
CPC分类号： G11C29/808 , G11C11/41 , G11C29/816
摘要： A method of assigning bits to redundant regions for variable bit redundancy region boundaries in a compliable memory such as a 1-port SRAM is provided. Methods include allocating bits between the redundant regions in nearly equal proportions while minimizing the amount of chip real estate consumed by the memory. Methods also includes allocating bits in equal portions between redundant regions while occupying slightly more memory chip real estate. Methods also allocate bits into redundant regions with a simplified procedure which may or may not allocate bits into the redundant regions in equal proportions. All of the methods allow the total number of memory bits in the complied memory to be re-defined while maintaining the same allocation characteristics for each method. Accordingly, the methods allow efficient use of redundant memory bits while also conserving chip real estate or offering simplified allocation steps.
摘要翻译：提供了一种将比特分配给诸如1端口SRAM的可复制存储器中的可变位冗余区域边界的冗余区域的方法。方法包括以几乎相等的比例在冗余区域之间分配比特，同时最小化存储器消耗的芯片空间的量。方法还包括在冗余区域之间相等分配比特，同时占据稍微更多的存储器芯片空间。方法还使用简化的过程将比特分配到冗余区域中，这可以或可以不以相等比例将比特分配到冗余区域中。所有这些方法允许重新定义编译存储器中的存储器位的总数，同时为每种方法保持相同的分配特性。因此，这些方法允许有效地使用冗余存储器位，同时还节省芯片空间或提供简化的分配步骤。

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