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    • 2. 发明申请
    • HALF CYCLE DELAY LOCKED LOOP AND ITS USE IN A FREQUENCY MULTIPLIER
    • 半周期延迟锁定环及其在频率乘法器中的使用
    • WO2012099992A1
    • 2012-07-26
    • PCT/US2012/021767
    • 2012-01-18
    • QUALCOMM INCORPORATEDYANG, Bo
    • YANG, Bo
    • H03L7/081H03L7/16
    • H03L7/0812H03L7/16
    • An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay introduced by the N delay elements is M/2. The integrated circuit also includes a plurality of inverters, each coupled to an output of one of the N delay elements, where the plurality is less than N. The integrated circuit also includes a phase detector coupled to the input node and an inverted Nth phase-shifted signal. The integrated circuit also includes a charge pump coupled to the phase detector and the delay elements.
    • 公开了一种用于半周期延迟锁定环路的集成电路。 集成电路包括耦合到具有M的时钟周期的振荡器的输入节点。该集成电路还包括输出N个不同相移信号的N个延迟元件,其中由N个延迟元件引入的总延迟为M / 2。 集成电路还包括多个反相器,每个反相器耦合到N个延迟元件中的一个的输出,其中多个小于N。该集成电路还包括耦合到输入节点的相位检测器和反相的第N相位滤波器, 移位信号。 集成电路还包括耦合到相位检测器和延迟元件的电荷泵。