专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008083901A1 MANAGING WRITE REQUESTS IN CACHE DIRECTED TO DIFFERENT STORAGE GROUPS 审中-公开
标题翻译：根据不同的存储组管理缓存中的写入请求
公开(公告)号：WO2008083901A1
公开(公告)日：2008-07-17
申请号：PCT/EP2007/064234
申请日：2007-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , GILL, Binny, Sher , BENHASE, Michael, Thomas , HYDE II, Joseph, Smith , JARVIS, Thomas, Charles , MCNUTT, Bruce , MODHA, Dharmendra, Shantilal
发明人： GILL, Binny, Sher , BENHASE, Michael, Thomas , HYDE II, Joseph, Smith , JARVIS, Thomas, Charles , MCNUTT, Bruce , MODHA, Dharmendra, Shantilal
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0873 , G06F12/121 , G06F2212/502
摘要： Provided are a method, system, and article of manufacture for managing write requests in cache directed to different storage groups. A determination is made of a high and low thresholds for a plurality of storage groups configured in a storage, wherein the high and low thresholds for one storage group indicate a high and low percentage of a cache that may be used to store write requests to the storage group. A determination is made of a number of tasks to assign to the storage groups based on the determined high and low thresholds for the storage groups, wherein each task assigned to one storage group destages write requests from the cache to the storage group.
摘要翻译：提供了一种用于管理针对不同存储组的缓存中的写请求的方法，系统和制品。确定在存储器中配置的多个存储组的高和低阈值，其中一个存储组的高和低阈值指示高速和低百分比的高速缓存，其可用于将写请求存储到存储组。基于确定的存储组的高和低阈值来确定分配给存储组的多个任务，其中分配给一个存储组的每个任务将来自高速缓存的写入请求转发到存储组。

2. 发明申请

WO2012055593A1 NEUROMORPHIC AND SYNAPTRONIC SPIKING NEURAL NETWORK WITH SYNAPTIC WEIGHTS LEARNED USING SIMULATION 审中-公开
标题翻译：神经网络和同步扫描神经网络与使用模拟学习的应激权重
公开(公告)号：WO2012055593A1
公开(公告)日：2012-05-03
申请号：PCT/EP2011/063485
申请日：2011-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MODHA, Dharmendra, Shantilal
发明人： MODHA, Dharmendra, Shantilal
IPC分类号： G01N3/10 , G06N3/063
CPC分类号： G06N3/08 , G06N3/04 , G06N3/049 , G06N3/063
摘要： Embodiments of the invention provide neuromorphic-synaptronic systems, including neuromorphic-synaptronic circuits implementing spiking neural network with synaptic weights learned using simulation. One embodiment includes simulating a spiking neural network to generate synaptic weights learned via the simulation while maintaining one-to- one correspondence between the simulation and a digital circuit chip. The learned synaptic weights are loaded into the digital circuit chip implementing a spiking neural network, the digital circuit chip comprising a neuromorphic-synaptronic spiking neural network including plural synapse devices interconnecting multiple digital neurons.
摘要翻译：本发明的实施方案提供神经形态 - synaptronic系统，其包括使用模拟学习的具有突触重量的尖峰神经网络的神经形态 - synaptronic电路。一个实施例包括模拟尖峰神经网络以产生通过模拟学习的突触权重，同时保持模拟和数字电路芯片之间的一对一对应关系。所学的突触权重被加载到实现尖峰神经网络的数字电路芯片中，该数字电路芯片包括一个包含多个连接多个数字神经元的突触装置的神经 - 突触间期刺激神经网络。

3. 发明申请

WO2010133399A1 ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING PHASE CHANGE MEMORY 审中-公开
标题翻译：使用相位变化记忆的具有SPIKE-TIMING相关塑性的电子学习
公开(公告)号：WO2010133399A1
公开(公告)日：2010-11-25
申请号：PCT/EP2010/054670
申请日：2010-04-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , RAJENDRAN, Bipin , BREITWISCH, Matthew, Joseph , LAM, Chung, Hon , CHEEK, Roger , MODHA, Dharmendra, Shantilal
发明人： RAJENDRAN, Bipin , BREITWISCH, Matthew, Joseph , LAM, Chung, Hon , CHEEK, Roger , MODHA, Dharmendra, Shantilal
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/049 , G06N3/0635 , G11C11/54 , G11C13/0004
摘要： A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.
摘要翻译：公开了一种用于在人造突触中产生尖峰依赖性可塑性的系统，方法和计算机程序产品。根据一个实施方案，用于在人造神经元中产生尖峰依赖性可塑性的方法包括当对第一神经元的总积分输入超过第一预定阈值时，在第一神经元中产生突触前尖峰事件。当到第二神经元的总积分输入超过第二预定阈值时，在第二神经元中产生突触后尖峰事件。在突触前尖峰事件之前，将第一脉冲施加到具有相变存储元件的突触的突触前突触节点。在突触后尖峰事件之后，将第二变化脉冲施加到突触的突触后结节，其中通过突触的电流是第一脉冲时的第二变化脉冲的状态的函数。

4. 发明申请

WO2012055592A1 COMPACT COGNITIVE SYNAPTIC COMPUTING CIRCUITS 审中-公开
标题翻译：紧凑的认知计算电路
公开(公告)号：WO2012055592A1
公开(公告)日：2012-05-03
申请号：PCT/EP2011/063400
申请日：2011-08-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MODHA, Dharmendra, Shantilal
发明人： MODHA, Dharmendra, Shantilal
IPC分类号： G06N3/10 , G06N3/063
CPC分类号： G06N3/063
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity using electronic neurons interconnected in a crossbar array network. The crossbar array network comprises a plurality of crossbar arrays. Each crossbar array comprises a plurality of axons and a plurality of dendrites such that the axons and dendrites are transverse to one another, and multiple synapse devices, wherein each synapse device is at a cross-point junction of the crossbar array coupled between a dendrite and an axon. The crossbar arrays are spatially in a staggered pattern providing a staggered crossbar layout of the synapse devices.
摘要翻译：本发明的实施例涉及使用在交叉开关阵列网络中互连的电子神经元来产生尖峰时序相关的可塑性。横杆阵列网络包括多个横杆阵列。每个横杆阵列包括多个轴突和多个树突，使得轴突和树突彼此横向，以及多个突触装置，其中每个突触装置处于交叉杆阵列的交叉点连接处，所述横杆阵列耦合在枝晶和一个轴突横杆阵列在空间上是交错的图案，提供突触装置的交错横截面布局。

5. 发明申请

WO2010133401A1 ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING MEMORY-SWITCHING ELEMENTS 审中-公开
标题翻译：使用存储器切换元件的SPIKE-TIMING相关塑料的电子学习实验
公开(公告)号：WO2010133401A1
公开(公告)日：2010-11-25
申请号：PCT/EP2010/054719
申请日：2010-04-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , SHENOY, Rohit, Sudhir , MODHA, Dharmendra, Shantilal
发明人： SHENOY, Rohit, Sudhir , MODHA, Dharmendra, Shantilal
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/049 , G06N3/0635
摘要： According to embodiments of the invention, a system, method and computer program product producing spike-dependent plasticity in an artificial synapse. In an embodiment, a method includes: receiving a pre-synaptic spike in an electronic component; receiving a post-synaptic spike in the electronic component; in response to the pre-synaptic spike, generating a pre-synaptic pulse that occurs a predetermined period of time after the received pre-synaptic spike; in response to the post-synaptic spike, generating a post-synaptic pulse that starts at a baseline value and reaches a first voltage value a first period of time after the post-synaptic spike, followed by a second voltage value a second period of time after the post synaptic spike, followed by a return to the baseline voltage a third period of time after the post-synaptic spike; applying the generated pre-synaptic pulse to a pre-synaptic node of a synaptic device that includes a uni-polar, two-terminal bi-stable device in series with a rectifying element; and applying the generated post-synaptic pulse to a post-synaptic node of the synaptic device, wherein the synaptic device changes from a first conductive state to a second conductive state based on the value of input voltage applied to its pre and post-synaptic nodes, wherein the resultant state of the conductance of the synaptic device after the pre- and post-synaptic pulses are applied thereto depends on the relative timing of the received pre-synaptic spike with respect to the post synaptic spike.
摘要翻译：根据本发明的实施例，在人造突触中产生尖峰依赖可塑性的系统，方法和计算机程序产品。在一个实施例中，一种方法包括：在电子部件中接收突触前突起; 接收电子元件中的突触后尖峰; 响应于突触前尖峰，产生在接收到的突触前尖峰之后发生预定时间段的突触前脉冲; 响应于突触后尖峰，产生在基线值开始并在突触后尖峰之后的第一时间段达到第一电压值的后突触后脉冲，随后是第二时间段的第二电压值后突触尖峰后，再次回到基线电压第三个时间段后突触后尖峰; 将产生的突触前脉冲应用于包括与整流元件串联的单极性双端双稳态器件的突触器件的突触前节点; 以及将所产生的突触后脉冲应用于所述突触装置的突触后结点，其中所述突触装置基于施加到其前和后突触节点的输入电压的值从第一导通状态改变到第二导通状态其中将突触前装置和突触后脉冲之后的突触装置的电导的结果状态施加到其上取决于所接收的突触前尖峰相对于突触后尖峰的相对时间。

6. 发明申请

WO2012089360A1 ELECTRONIC SYNAPSES FOR REINFORCEMENT LEARNING 审中-公开
标题翻译：用于加强学习的电子技术
公开(公告)号：WO2012089360A1
公开(公告)日：2012-07-05
申请号：PCT/EP2011/068183
申请日：2011-10-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MODHA, Dharmendra, Shantilal , CHANG, Leland , MONTOYE, Robert, Kevin
发明人： MODHA, Dharmendra, Shantilal , CHANG, Leland , MONTOYE, Robert, Kevin
IPC分类号： G06N3/063
CPC分类号： G06N3/08 , G06N3/063 , G06N3/0635 , G11C11/54
摘要： Embodiments of the invention provide electronic synapse devices for reinforcement learning. An electronic synapse is configured for interconnecting a pre-synaptic electronic neuron and a post-synaptic electronic neuron. The electronic synapse comprises memory elements configured for storing a state of the electronic synapse and storing meta information for updating the state of the electronic synapse. The electronic synapse further comprises an update module configured for updating the state of the electronic synapse based on the meta information in response to an update signal for reinforcement learning. The update module is configured for updating the state of the electronic synapse based on the meta information, in response to a delayed update signal for reinforcement learning based on a learning rule.
摘要翻译：本发明的实施例提供用于加强学习的电子突触装置。配置电子突触以互连预突触电子神经元和突触后电子神经元。电子突触包括配置用于存储电子突触的状态并存储用于更新电子突触的状态的元信息的存储器元件。电子突变还包括更新模块，该更新模块被配置为响应于用于加强学习的更新信号，基于元信息来更新电子突触的状态。更新模块被配置为响应于用于基于学习规则的加强学习的延迟更新信号，基于元信息来更新电子突触的状态。

7. 发明申请

WO2012000698A1 CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY 审中-公开
标题翻译：经典SPIKING神经网络的空间相关记忆
公开(公告)号：WO2012000698A1
公开(公告)日：2012-01-05
申请号：PCT/EP2011/056701
申请日：2011-04-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , NDIRANGO, Anthony , MODHA, Dharmendra, Shantilal , ESSER, Steve, Kyle
发明人： NDIRANGO, Anthony , MODHA, Dharmendra, Shantilal , ESSER, Steve, Kyle
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.
摘要翻译：本发明的实施例涉及用于时空关联记忆的规范加标神经元。本发明的一个方面提供了包括具有与定向突触连通性的分层神经网络关系的多个电子神经元的时空相关存储器。多个电子神经元被配置为检测实时数据流中的时空模式的存在，并提取时空模式。多个电子神经元还被配置为基于学习规则将时空图案存储在多个电子神经元中，并且在呈现时空图案的版本时，检索存储的时空图案。

8. 发明申请

WO2011060973A1 AREA EFFICIENT NEUROMORPHIC CIRCUITS 审中-公开
标题翻译：区域有效的神经电路
公开(公告)号：WO2011060973A1
公开(公告)日：2011-05-26
申请号：PCT/EP2010/062368
申请日：2010-08-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BREITWISCH, Matthew, Joseph , LAM, Chung, Hon , MODHA, Dharmendra, Shantilal , RAJENDRAN, Bipin
发明人： BREITWISCH, Matthew, Joseph , LAM, Chung, Hon , MODHA, Dharmendra, Shantilal , RAJENDRAN, Bipin
IPC分类号： G06N3/063 , G11C11/56 , H01L27/28
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.
摘要翻译：神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点神经元电路。

9. 发明申请

WO2014080300A1 NEURAL NETWORK 审中-公开
标题翻译：神经网络
公开(公告)号：WO2014080300A1
公开(公告)日：2014-05-30
申请号：PCT/IB2013/056734
申请日：2013-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： ALVAREZ-ICAZA RIVERA, Rodrigo , ARTHUR, John, Vernon , CASSIDY, Andrew, Stephen , MEROLLA, Paul , MODHA, Dharmendra, Shantilal
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/04 , G06N3/063
摘要： A neural network system includes a memory array that maintains information for multiple neurosynaptic core modules wherein each neurosynaptic core module comprises multiple neurons. The neural network system further comprises at least one logic circuit, wherein each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory for said neurosynaptic core module.
摘要翻译：神经网络系统包括维持多个神经突触核心模块的信息的存储器阵列，其中每个神经突触核心模块包括多个神经元。所述神经网络系统还包括至少一个逻辑电路，其中每个逻辑电路接收针对所述神经网络系统的神经突触核心模块的神经元触发事件，并且所述逻辑电路基于所述存储器中保存的所述神经轴突的信息来集成所接收的触发事件核心模块。

10. 发明申请

WO2014135298A2 STRUCTURAL DESCRIPTIONS FOR NEUROSYNAPTIC NETWORKS 审中-公开
标题翻译：神经网络的结构描述
公开(公告)号：WO2014135298A2
公开(公告)日：2014-09-12
申请号：PCT/EP2014/051215
申请日：2014-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： MODHA, Dharmendra, Shantilal
IPC分类号： G06N3/063
CPC分类号： G06N3/063 , G06N3/02 , G06N3/04 , G06N3/049 , G06N3/10
摘要： Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits.
摘要翻译：本发明的实施例提供了一种方法，其包括为至少一个神经突触核心电路创建结构描述。每个核心电路包括互连网络，其包括用于将一个或多个电子神经元与一个或多个电子轴突互连的多个电子突触。结构描述定义了核心电路所需的神经元活动。通过用结构描述对核心电路进行编程来模拟所需的神经元活动。结构描述控制核心电路的神经元发射事件的路由。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式