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1. 发明申请

WO2013064935A1 DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE 审中-公开
标题翻译：动态调整二级缓存的人口数量
公开(公告)号：WO2013064935A1
公开(公告)日：2013-05-10
申请号：PCT/IB2012/055730
申请日：2012-10-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： GUPTA, Lokesh, Mohan , ELEFTHERIOU, Evangelos, Stravros , KOLTSIDAS, Ioannis , HU, Xiao-Yu , PLETKA, Roman , HAAS, Robert , BLINICK, Stephen , BENHASE, Michael, Thomas
IPC分类号： G06F12/12 , G06F3/06
CPC分类号： G06F12/0888 , G06F12/0866 , G06F12/0897 , G06F2212/225
摘要： The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose heat metric is equal to or greater than the heat metric threshold. The adjustment of the heat metric threshold is determined by comparing a reference metric related to hits of data most recently inserted into the secondary data storage cache, to a reference metric related to hits of data most recently evicted from the secondary data storage cache; if the most recently inserted reference metric is greater than the most recently evicted reference metric, decrementing the threshold; and if the most recently inserted reference metric is less than the most recently evicted reference metric, incrementing the threshold.
摘要翻译：通过确定候选数据的热度量来控制要插入到辅助数据存储高速缓存中的数据的总数; 调整热量度量阈值; 拒绝提供给热度量小于阈值的次数据存储高速缓存的候选数据; 并且允许其热度量等于或大于热度量阈值的候选数据。通过将与最近插入次级数据存储高速缓存中的数据的命中相关的参考度量与与次级数据存储高速缓存最近被排出的数据的命中相关的参考度量进行比较来确定热度量阈值的调整; 如果最近插入的参考度量值大于最近被驱逐的参考度量，则递减阈值; 并且如果最近插入的参考度量小于最近驱逐的参考度量，则递增阈值。

2. 发明申请

WO2013132370A1 ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM 审中-公开
标题翻译：自适应高速缓存在两级缓存系统中的推广
公开(公告)号：WO2013132370A1
公开(公告)日：2013-09-12
申请号：PCT/IB2013/051313
申请日：2013-02-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： GUPTA, Lokesh, Mohan , ELEFTHERIOU, Evangelos, Stavros , KOLTSIDAS, Ioannis , HU, Xiao-Yu , PLETKA, Roman , HAAS, Robert , BLINICK, Stephen , BENHASE, Michael, Thomas
IPC分类号： G06F12/12 , G06F3/06 , G06F12/08
CPC分类号： G06F12/128 , G06F12/126
摘要： Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (MRU) end of the LRU list in the first cache.
摘要翻译：提供了一种用于管理第一高速缓存和第二高速缓存中的数据的计算机程序产品，系统和方法。当页面存储在第二高速缓存中时，对于页面的第二高速缓存中维护引用计数。确定页面将被从第二缓存提升到第一高速缓存。响应于确定参考计数大于零，该页被添加到第一高速缓存中的LRU列表的最近最少使用（LRU）末端。响应于确定参考计数小于或等于零，该页面被添加到第一高速缓存中的LRU列表的最近使用（MRU）端。

3. 发明申请

WO2013064917A1 PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE 审中-公开
标题翻译：在FLASH CACHE中推广部分数据段
公开(公告)号：WO2013064917A1
公开(公告)日：2013-05-10
申请号：PCT/IB2012/054460
申请日：2012-08-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED , GUPTA, Lokesh, Mohan , ELEFTHERIOU, Evangelos, Stavros , KOLTSIDAS, Ioannis , HU, Xiao-Yu , PLETKA, Roman , HAAS, Robert , BLINICK, Stephen , KALOS, Matthew, Joseph , NIELSEN, Karl, Allen , BENHASE, Michael, Thomas
发明人： GUPTA, Lokesh, Mohan , ELEFTHERIOU, Evangelos, Stavros , KOLTSIDAS, Ioannis , HU, Xiao-Yu , PLETKA, Roman , HAAS, Robert , BLINICK, Stephen , KALOS, Matthew, Joseph , NIELSEN, Karl, Allen , BENHASE, Michael, Thomas
IPC分类号： G06F12/08
CPC分类号： G06F3/0619 , G06F3/0646 , G06F3/0688 , G06F12/0246 , G06F12/0253 , G06F12/0811 , G06F12/0862 , G06F12/0864 , G06F12/0871 , G06F12/0897 , G06F12/122 , G06F12/127 , G06F12/128 , G06F2212/1016 , G06F2212/154 , G06F2212/222 , G06F2212/283 , G06F2212/604 , G06F2212/702 , G06F2212/7201
摘要： Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. Additional system and computer program product embodiments are disclosed and provide related advantages.
摘要翻译：提供了用于以更有效的方式在二次存储中有效地追踪排水的示例性方法，系统和计算机程序产品实施例。在一个实施例中，仅作为示例，对于与用于控制主存储器中的跟踪的定时的顺序位一起使用的时间位，时间位和顺序位从主存储器传送到次存储器。时间位允许在辅助存储器上老化。公开了附加的系统和计算机程序产品实施例并提供相关的优点。

4. 发明申请

WO2013064936A1 METHOD AND SYSTEM FOR SELECTIVE SPACE RECLAMATION OF DATA STORAGE MEMORY EMPLOYING HEAT AND RELOCATION METRICS 审中-公开
标题翻译：选择性空间回收数据存储器的方法和系统采用热和转移量度
公开(公告)号：WO2013064936A1
公开(公告)日：2013-05-10
申请号：PCT/IB2012/055801
申请日：2012-10-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： GUPTA, Lokesh, Mohan , ELEFTHERIOU, Evangelos, Stavros , KOLTSIDAS, Ioannis , HU, Xiao-Yu , PLETKA, Roman , HAAS, Robert , BENHASE, Michael, Thomas , KALOS, Matthew, Joseph
IPC分类号： G06F12/06
CPC分类号： G06F12/122 , G06F3/0608 , G06F3/0652 , G06F3/0683 , G06F12/0253 , G06F12/0871 , G06F12/121 , G06F12/126 , G06F12/128 , G06F2212/222 , G06F2212/7205
摘要： A method and computer program product for reclaiming space of a data storage memory of a data storage memory system, and a computer-implemented data storage memory system are provided. The method includes: determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation. Thus, data that otherwise may be evicted or demoted, but that meets or exceeds the utility metric threshold, is exempted from space reclamation and is instead maintained in the data storage memory.
摘要翻译：提供了一种用于回收数据存储存储器系统的数据存储器的空间的方法和计算机程序产品，以及计算机实现的数据存储存储器系统。该方法包括：确定存储在数据存储存储器中的数据的热量度; 确定与数据存储存储器内的数据的重新定位相关的重定位度量; 将与所述热量度量相关的数据的效用度量确定为所述数据的重定位度量; 并使其实用度量值的数据失效，可用于空间回收。因此，否则可能被逐出或降级但满足或超过效用度量阈值的数据被免除空间回收，而是保留在数据存储存储器中。

5. 发明申请

WO2011070526A1 FLASH MEMORY CONTROLLER 审中-公开
标题翻译：闪存控制器
公开(公告)号：WO2011070526A1
公开(公告)日：2011-06-16
申请号：PCT/IB2010/055684
申请日：2010-12-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu
IPC分类号： G06F13/16
CPC分类号： G06F13/1668 , G06F9/3004 , G11C7/1042
摘要： A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.
摘要翻译：闪存控制器通过第一闪存存储器接口耦合到第一闪存存储器封装，并通过第一闪存存储器接口耦合到第二闪存存储器封装。闪存控制器被设计为接收与第一闪存存储器包相关的第一指令，并且根据第一指令执行第一处理。闪存控制器还被设计为接收与第二闪存存储器包相关的第二指令，并且根据第二指令执行第二处理。闪存控制器还适用于将第一进程分成至少两个第一子步骤，并将第二进程分成至少两个第二子步骤。闪存控制器还适用于执行第一和第二子步骤，并且用于交错执行第一和第二子步骤。

6. 发明申请

WO2011073940A1 DATA MANAGEMENT IN SOLID STATE STORAGE SYSTEMS 审中-公开
标题翻译：固态存储系统中的数据管理
公开(公告)号：WO2011073940A1
公开(公告)日：2011-06-23
申请号：PCT/IB2010/055875
申请日：2010-12-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias , MITTELHOLZER, Thomas
发明人： CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias , MITTELHOLZER, Thomas
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , G06F11/1068 , G06F11/108
摘要： Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage (6) of a solid state storage system (5). Input data is stored in successive groups of data write locations in the solid state storage (6). Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage (6). The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords. The encoding and storage operation is performed such that, in each said group, the encoded input data comprises a plurality of first codewords in each of a plurality of the logical subdivisions and each logical subdivision contains a portion of each of the second codewords for that group.
摘要翻译：提供了用于控制数据管理操作的方法和装置，包括在固态存储系统（5）的固态存储（6）中存储数据。输入数据存储在固态存储器（6）中的连续的数据写入位置组中。每个组包括在固态存储器（6）的多个逻辑子部分中的每一个中的一组写入位置。要存储在每个组中的输入数据根据第一和第二线性纠错码进行编码。通过从输入数据中构成数据符号的行和列的逻辑阵列，来构成编码。行和列分别根据第一和第二线性纠错码编码以产生编码阵列，其中所有行对应于相应的第一码字和列对应于相应的第二码字。执行编码和存储操作，使得在每个所述组中，编码的输入数据包括多个逻辑子部分中的每一个中的多个第一码字，并且每个逻辑细分包含该组的每个第二码字的一部分。

7. 发明申请

WO2012014140A2 LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES 审中-公开
标题翻译：在包含固态存储器件的存储系统中逻辑地址映射
公开(公告)号：WO2012014140A2
公开(公告)日：2012-02-02
申请号：PCT/IB2011/053299
申请日：2011-07-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BUX, Werner , HAAS, Robert , HU, Xiaoyu , PLETKA, Roman, A.
发明人： BUX, Werner , HAAS, Robert , HU, Xiaoyu , PLETKA, Roman, A.
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0848 , G06F12/0866 , G06F2212/214 , G06F2212/221 , G06F2212/222 , G06F2212/466 , G06F2212/7201
摘要： The present idea provides a high read and write performance from/to a solid state memory device. The main memory (31) of the controller (1) is not blocked by a complete address mapping table covering the entire memory device (2). Instead such table is stored in the memory device (2) itself, and only selected portions of address mapping information are buffered in the main memory (31) in a read cache (311) and a write cache (312). A separation of the read cache (311) from the write cache (312) enables an address mapping entry being evictable from the read cache (311) without the need to update the related flash memory page storing such entry in the flash memory device (2). By this design, the read cache (311) may advantageously be stored on a DRAM even without power down protection, while the write cache (312) may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.
摘要翻译：本想法提供了从/到固态存储器件的高读/写性能。控制器（1）的主存储器（31）不被覆盖整个存储器件（2）的完整地址映射表阻塞。相反，这样的表被存储在存储器件（2）本身中，并且只有地址映射信息的选择部分被缓存在读取高速缓存（311）和写入高速缓存（312）中的主存储器（31）中。读取高速缓存（311）与写入高速缓存（312）的分离使得能够从读取的高速缓存（311）中消除地址映射条目，而不需要在闪存设备（2）中更新存储这样的条目的相关闪存页面）。通过该设计，即使没有掉电保护，读高速缓存（311）也可有利地存储在DRAM上，而写高速缓存（312）可优选地被实现在非易失性或其他故障安全存储器中。这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。

8. 发明申请

WO2012001556A1 WEAR-LEVELING OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY 审中-公开
标题翻译：细胞/页/子页/记忆块的磨损等级
公开(公告)号：WO2012001556A1
公开(公告)日：2012-01-05
申请号：PCT/IB2011/052492
申请日：2011-06-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy, Daron , ELEFTHERIOU, Evangelos, S. , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias , PLETKA, Roman, A.
发明人： CIDECIYAN, Roy, Daron , ELEFTHERIOU, Evangelos, S. , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias , PLETKA, Roman, A.
IPC分类号： G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： The invention is directed to a method for wear-leveling cells or pages or sub- pages or blocks of a memory such as a flash memory, the method comprising: - receiving (S10) a chunk of data to be written on a cell or page or sub-page or block of the memory; - counting (S40) in the received chunk of data the number of times a given type of binary data '0' or Ί ' is to be written; and - distributing (S50) the writing of the received chunk of data amongst cells or pages or sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data '0' or Ί ' counted in the chunk of data to be written.
摘要翻译：本发明涉及一种用于对诸如闪速存储器之类的存储器的单元格或页面或子页面或块进行磨损均衡的方法，所述方法包括： - 接收（S10）要写入单元或页面的数据块或子页或块的存储器; - 在接收到的数据块中计数（S40）次数给定类型的二进制数据“0”或？ “要写以及 - 分配（S50）在存储器的单元格或页面或子页面或块之间写入所接收的数据块，以便相对于给定类型的二进制数据“0”的数量对存储器进行磨损级别要么？ “在数据块中计算要写入。

9. 发明申请

WO2011151759A1 DECODING OF LDPC CODE 审中-公开
标题翻译： LDPC码的解码
公开(公告)号：WO2011151759A1
公开(公告)日：2011-12-08
申请号：PCT/IB2011/052268
申请日：2011-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu , NGUYEN, Dung Viet
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu , NGUYEN, Dung Viet
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态来设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

10. 发明申请

WO2011101178A1 INTEGRATING A FLASH CACHE INTO LARGE STORAGE SYSTEMS 审中-公开
标题翻译：将闪存集成到大型存储系统中
公开(公告)号：WO2011101178A1
公开(公告)日：2011-08-25
申请号：PCT/EP2011/050154
申请日：2011-01-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PLETKA, Roman , ELEFTHERIOU, Evangelos , HAAS, Robert , HU, Xiao-Yu , HSU, Yu-Cheng , GUPTA, Lokesh, Mohan , HYDE II, Joseph, Smith , BENHASE, Michael, Thomas , SANCHEZ, Alfred, Emilio , ASH, Kevin, John
发明人： PLETKA, Roman , ELEFTHERIOU, Evangelos , HAAS, Robert , HU, Xiao-Yu , HSU, Yu-Cheng , GUPTA, Lokesh, Mohan , HYDE II, Joseph, Smith , BENHASE, Michael, Thomas , SANCHEZ, Alfred, Emilio , ASH, Kevin, John
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F3/0611 , G06F3/0655 , G06F3/0685 , G06F2212/214 , G06F2212/2146
摘要： An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.
摘要翻译： I / O机箱模块设置有一个或多个具有多个用于接收电子设备的插槽的I / O机箱。主机适配器连接在I / O机箱模块的第一个插槽上，并配置为将主机连接到I / O机箱。设备适配器连接到I / O机箱模块的第二个插槽，并配置为将存储设备连接到I / O机柜模块。闪存缓存连接到I / O机箱模块的第三个插槽，并且包括配置为缓存与通过I / O机箱模块处理的数据请求相关联的数据的基于闪存的存储器。主处理器复合体通过与主机适配器，设备适配器和闪存缓存进行通信来管理通过I / O机箱模块处理的数据请求，以管理数据请求。

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