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1. 发明申请

WO2022018038A1 SUPERCONDUCTING STRUCTURE AND DEVICE SURFACE TERMINATION WITH ALLOY 审中-公开
公开(公告)号：WO2022018038A1
公开(公告)日：2022-01-27
申请号：PCT/EP2021/070173
申请日：2021-07-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： WYMORE, Benjamin , LAVOIE, Christian , BRINK, Markus
IPC分类号： H01L39/24
摘要： A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the first metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layerand the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

2. 发明申请

WO2022037956A1 GRAIN SIZE CONTROL OF SUPERCONDUCTING THIN FILM MATERIALS FOR JOSEPHSON|JUNCTIONS 审中-公开
公开(公告)号：WO2022037956A1
公开(公告)日：2022-02-24
申请号：PCT/EP2021/071868
申请日：2021-08-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： WYMORE, Benjamin , LAVOIE, Christian , BRINK, Markus , BRULEY, John
IPC分类号： H01L39/22 , H01L39/24
摘要： The disclosed Josephson junction device (110) includes a lower superconducting layer (210) formed on a substrate (220), a junction layer (240) formed on the lower superconducting material layer, and an upper superconducting layer (230) formed over the junction layer, wherein at least the lower superconducting layer comprises grains having a size that is larger than a size (260) of a Josephson junction. Alternatively, the lower superconducting layer is an alloy, preferably of Al, having an average grain size less than 20 nm and smaller than a length and width of the junction.

3. 发明申请

WO2015145274A1 OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION 审中-公开
标题翻译：氧化物介质的外延镍基合金接触形成
公开(公告)号：WO2015145274A1
公开(公告)日：2015-10-01
申请号：PCT/IB2015/051263
申请日：2015-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： OZCAN, Ahmet, Serkan , BREIL, Nicolas , ALPTEKIN, Emre , SCHONENBERG, Kathryn , LAVOIE, Christian
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/76886 , H01L21/28518 , H01L21/28568 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L21/76895 , H01L21/823871 , H01L23/485 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/092 , H01L29/41766 , H01L29/665 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.
摘要翻译：接触开口形成为露出半导体衬底的表面部分的电介质材料。然后在每个接触开口中和界面氧化物层的暴露表面部分上形成界面氧化物层。在每个开口内和每个界面氧化物层的暴露的表面部分上形成NiPt合金层。然后进行退火，其形成从底部到顶部具有倒金字塔形状，富Pt硅化物帽区域和富氧区域的二硅化镍合金体的接触结构。然后在每个接触开口内和每个接触结构的富氧区顶上形成金属接触。

4. 发明申请

WO2007133356A1 METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS 审中-公开
标题翻译：形成自对准金属硅化物接触的方法
公开(公告)号：WO2007133356A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/008798
申请日：2007-04-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FANG, Sunfei , KNARR, Randolph, F. , KRISHNAN, Mahadevaiyer , LAVOIE, Christian , MO, Renee, T. , PRANATHARTHIHARAN, Balasubramanian , STRANE, Jay, W.
发明人： FANG, Sunfei , KNARR, Randolph, F. , KRISHNAN, Mahadevaiyer , LAVOIE, Christian , MO, Renee, T. , PRANATHARTHIHARAN, Balasubramanian , STRANE, Jay, W.
IPC分类号： H01L21/44 , C23F1/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： A method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region is disclosed. Each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region, is essentially free of metal and metal silicide. Nickel or nickel alloy deposition is followed by low-temperature annealing, nickel etching, high-temperature annealing, and aqua regla etching.
摘要翻译：公开了一种用于在通过暴露的电介质区域彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的硅化镍和硅化铂，并且暴露的电介质区域基本上不含金属和金属硅化物。镍或镍合金沉积之后是低温退火，镍蚀刻，高温退火和水蚀刻蚀刻。

5. 发明申请

WO2006072538A1 SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS 审中-公开
标题翻译： NANOTUBE / NANOWIRE FET的自对准工艺
公开(公告)号：WO2006072538A1
公开(公告)日：2006-07-13
申请号：PCT/EP2005/056746
申请日：2005-12-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , AVOURIS, Phaedon , CARRUTHERS, Roy , CHEN, Jia , DETAVERNIER, Christophe , LAVOIE, Christian , WONG, Hon-sum Philip
发明人： AVOURIS, Phaedon , CARRUTHERS, Roy , CHEN, Jia , DETAVERNIER, Christophe , LAVOIE, Christian , WONG, Hon-sum Philip
IPC分类号： H01L51/00
CPC分类号： H01L29/6656 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/665 , H01L29/7833 , H01L51/0048 , H01L51/0541 , Y10S977/847 , Y10S977/938
摘要： A semiconductor structure comprising: a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure; and a metal carbide contact located on a surface of said substrate that is aligned to an edge of said layer of at least one one-dimensional nanostructure.
摘要翻译：一种半导体结构，包括：衬底，其包括位于其上的至少一个栅极区域，所述至少一个栅极区域包括至少一个一维纳米结构层; 以及金属碳化物接触件，位于所述衬底的与至少一个一维纳米结构的所述层的边缘对准的表面上。

6. 发明申请

WO2006015912A1 MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS 审中-公开
标题翻译：具有多个自对准硅化物接触的MOSFET结构
公开(公告)号：WO2006015912A1
公开(公告)日：2006-02-16
申请号：PCT/EP2005/053082
申请日：2005-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHAN, Kevin , LAVOIE, Christian , RIM, Kern
发明人： CHAN, Kevin , LAVOIE, Christian , RIM, Kern
IPC分类号： H01L21/336
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor (14) having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide (32) having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide (30) located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管（14），其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物（32），其具有基本上对准所述至少一个金属氧化物半导体场效应晶体管的栅极边缘的边缘; 以及位于第一内部硅化物附近的第二外部硅化物（30）。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

7. 发明申请

WO2015118417A1 METAL SEMICONDUCTOR ALLOY CONTACT RESISTANCE IMPROVEMENT 审中-公开
标题翻译：金属半导体合金接触电阻改进
公开(公告)号：WO2015118417A1
公开(公告)日：2015-08-13
申请号：PCT/IB2015/050147
申请日：2015-01-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： BREIL, Nicolas , OZCAN, Ahmet, Serkan , ALPTEKIN, Emre , LAVOIE, Christian , SCHONENBERG, Kathryn
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28026 , H01L21/28512 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L23/485 , H01L23/53238 , H01L29/456 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element.
摘要翻译：接触开口形成为露出半导体衬底的表面部分的电介质材料。包括至少一个第一过渡金属元件的第一过渡金属衬垫，包括与所述至少一个第一过渡金属元件不同的至少一个第二过渡金属元件和金属接触件的第二过渡金属衬垫在每个接触开口。在平坦化处理之后，结构是在每个接触开口的底部处退火形成金属半导体合金触点。形成的每个金属半导体合金触点包括至少一个第一过渡金属元件，至少一个第二过渡金属元件和半导体元件。

8. 发明申请

WO2012109079A1 A METHOD TO ENABLE THE PROCESS AND ENLARGE THE PROCESS WINDOW FOR SILICIDE, GERMANIDE OR GERMANOSILICIDE FORMATION IN STRUCTURES WITH EXTREMELY SMALL DIMENSIONS 审中-公开
标题翻译：一种使用过程的方法，并扩大了具有极小尺寸结构的硅酮，锗化物或锗氰酸酯形成的工艺窗口
公开(公告)号：WO2012109079A1
公开(公告)日：2012-08-16
申请号：PCT/US2012/023569
申请日：2012-02-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FLETCHER, Benjamin Luke , LAVOIE, Christian , MAURER, Siegfried Lutz , ZHANG, Zhen
发明人： FLETCHER, Benjamin Luke , LAVOIE, Christian , MAURER, Siegfried Lutz , ZHANG, Zhen
IPC分类号： H01L21/44
CPC分类号： B82Y40/00 , B82Y10/00 , H01L29/0673 , H01L29/16 , H01L29/66469 , H01L29/775
摘要： Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.
摘要翻译：提供了极小结构中硅化物，锗化锗或锗硅化物形成技术。一方面，提供了在具有极小尺寸的三维硅，锗或硅锗结构中形成硅化物，锗化锗或锗硅化物的方法。该方法包括以下步骤。将至少一个元件植入结构中。至少一种金属沉积在结构上。将该结构退火以将硅，锗或硅锗内的金属分散以形成硅化物，锗化锗或锗硅化物，其中所述植入元件用于防止硅化物，锗化物或锗硅化物的形态降解。植入元件可以包括碳，氟和硅中的至少一种。

9. 发明申请

WO2011064085A1 SELF ALIGNED CARBIDE SOURCE/DRAIN FET 审中-公开
标题翻译：自对准碳源/漏极FET
公开(公告)号：WO2011064085A1
公开(公告)日：2011-06-03
申请号：PCT/EP2010/066989
申请日：2010-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHANG, Josephine , GUILLORN, Michael , LAVOIE, Christian , CABRAL, Cyril, Jr. , GRILL, Alfred , O'SULLIVAN, Eugene
发明人： CHANG, Josephine , GUILLORN, Michael , LAVOIE, Christian , CABRAL, Cyril, Jr. , GRILL, Alfred , O'SULLIVAN, Eugene
IPC分类号： H01L29/775 , H01L29/16 , H01L51/05
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide drain portion, a nanostructure formed over the insulating carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物排出部分分离的绝缘碳部分，形成在绝缘碳部分上并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分和至少一部分纳米结构的至少一部分上的栅叠层。

10. 发明申请

WO2011056313A2 STRUCTURE AND METHOD TO FORM A THERMALLY STALE SILICIDE IN NARROW DIMENSION GATE STACKS 审中-公开
标题翻译：在窄尺寸盖板中形成热稳定性硅的结构和方法
公开(公告)号：WO2011056313A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/049901
申请日：2010-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , OZCAN, Ahmet, S. , LAVOIE, Christian , DOMENICUCCI, Anthony, G.
发明人： OZCAN, Ahmet, S. , LAVOIE, Christian , DOMENICUCCI, Anthony, G.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/66507 , H01L29/6653 , H01L29/6659
摘要： An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a suicide region comprising Pt segregated in a region of the suicide away from the top surface of the suicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the suicide. The suicide is first formed by a formation anneal, at a temperature in the range 250°C to 450°C. Subsequently, a segregation anneal at a temperature in the range 450°C to 550°C. The distribution of the Pt along the vertical length of the suicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the suicide layer and the pulldown spacer height.
摘要翻译：提供了一种集成电路，其包括具有小于或等于65nm的宽度的窄栅极堆叠，包括在硅化物远离硅化物的顶表面的区域中分离出Pt并且朝向由硅化物在栅极导体的侧壁上的间隔物的下拉高度。在优选实施例中，在形成自杀之前将间隔物拉下。首先通过地层退火在250℃至450℃的温度范围内形成自杀。随后，在450℃至550℃范围内的温度下进行偏析退火。沿着硅化物层的垂直长度的Pt的分布在分离区域内具有峰值Pt浓度，并且偏析的Pt区域具有小于峰值Pt浓度的一半的宽度，其小于顶表面之间的距离的50％的自杀层和下拉垫片高度。

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