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1. 发明授权

US10784333B2 Electronic devices having spiral conductive structures 有权
公开(公告)号：US10784333B2
公开(公告)日：2020-09-22
申请号：US16456610
申请日：2019-06-28
申请人： International Business Machines Corporation
发明人： Peng Xu , Kangguo Cheng , Xuefeng Liu , Chi-Chun Liu , Yongan Xu
IPC分类号： H01L49/02 , H01L21/3105 , H01L23/522
摘要： Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

2. 发明授权

US10699959B2 Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors 有权
公开(公告)号：US10699959B2
公开(公告)日：2020-06-30
申请号：US16396198
申请日：2019-04-26
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Xuefeng Liu , Heng Wu , Peng Xu
IPC分类号： H01L21/8234 , H01L49/02 , H01L27/06 , H01L29/78 , H01L29/66 , H01L21/822
摘要： Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

3. 发明授权

US10504889B1 Integrating a junction field effect transistor into a vertical field effect transistor 有权
公开(公告)号：US10504889B1
公开(公告)日：2019-12-10
申请号：US16037072
申请日：2018-07-17
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Huiming Bu , Terence B. Hook , Xuefeng Liu , Junli Wang
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/66 , H01L29/423 , H01L21/762 , H01L29/78 , H01L29/808 , H01L29/10 , H01L29/08 , H01L21/3105 , H01L29/36 , H01L29/167 , H01L29/04 , H01L21/033
CPC分类号： H01L27/0617 , H01L21/76224 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L29/0843 , H01L29/0847 , H01L29/1037 , H01L29/1058 , H01L29/42316 , H01L29/42376 , H01L29/6656 , H01L29/66909 , H01L29/7827 , H01L29/8083 , H01L21/0332 , H01L21/0337 , H01L21/31053 , H01L29/045 , H01L29/167 , H01L29/36
摘要： Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

4. 发明申请

US20190341444A1 ELECTRONIC DEVICES HAVING SPIRAL CONDUCTIVE STRUCTURES 审中-公开
公开(公告)号：US20190341444A1
公开(公告)日：2019-11-07
申请号：US16456610
申请日：2019-06-28
申请人： International Business Machines Corporation
发明人： Peng Xu , Kangguo Cheng , Xuefeng Liu , Chi-Chun Liu , Yongan Xu
IPC分类号： H01L49/02 , H01L21/3105
摘要： Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

5. 发明申请

US20190259666A1 INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：US20190259666A1
公开(公告)日：2019-08-22
申请号：US16396013
申请日：2019-04-26
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Xuefeng Liu , Heng Wu , Peng Xu
IPC分类号： H01L21/8234 , H01L29/66 , H01L21/822 , H01L29/78 , H01L27/06 , H01L49/02
摘要： Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

6. 发明授权

US09991365B1 Forming vertical transport field effect transistors with uniform bottom spacer thickness 有权
公开(公告)号：US09991365B1
公开(公告)日：2018-06-05
申请号：US15498112
申请日：2017-04-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Xuefeng Liu , Peng Xu , Yongan Xu
IPC分类号： H01L21/82 , H01L29/66 , H01L29/10 , H01L29/08 , H01L21/02 , H01L29/06 , H01L29/78 , H01L29/423
CPC分类号： H01L29/66666 , H01L21/02164 , H01L21/02238 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/42376 , H01L29/6653 , H01L29/66553 , H01L29/6656 , H01L29/7827
摘要： A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

7. 发明授权

US09786656B1 Integration of bipolar transistor into complimentary metal-oxide-semiconductor process 有权
公开(公告)号：US09786656B1
公开(公告)日：2017-10-10
申请号：US15241348
申请日：2016-08-19
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Xuefeng Liu , Junli Wang
IPC分类号： H01L21/8222 , H01L27/06 , H01L29/66 , H01L21/8249 , H01L29/08 , H01L29/06 , H01L29/165 , H01L29/167 , H01L21/02 , H01L21/306 , H01L29/45 , H01L29/78 , H01L29/737
CPC分类号： H01L27/0623 , H01L21/02532 , H01L21/30604 , H01L21/8249 , H01L29/0657 , H01L29/0692 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/165 , H01L29/167 , H01L29/456 , H01L29/66242 , H01L29/66272 , H01L29/66795 , H01L29/7371 , H01L29/7851
摘要： A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer.

8. 发明授权

US09404960B2 On chip bias temperature instability characterization of a semiconductor device 有权
标题翻译：半导体器件的片上偏置温度不稳定性表征
公开(公告)号：US09404960B2
公开(公告)日：2016-08-02
申请号：US14041422
申请日：2013-09-30
申请人： International Business Machines Corporation
发明人： Hanyi Ding , Xuefeng Liu , Alvin W. Strong , Randy L. Wolf
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2628 , G01R31/2623 , G01R31/2822
摘要： Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.
摘要翻译：本发明的实施例提供了表征偏压温度不稳定性对半导体器件的影响的电路和方法。电路包括具有栅，漏，源和体端子的晶体管。两个AC焊盘组均具有多个导电焊盘。两个直流焊盘与直流电源和/或电表通讯。栅极端子与包括在每个AC焊盘组的多个导电焊盘中的第一导电焊盘连通。漏极端子与AC焊盘组的第二导电焊盘和源极端子与另一个AC焊盘组的第二导电焊盘连通。一个直流焊盘通过第一串联电阻器与栅极端子连通，另一个直流焊盘通过第二串联电阻器与主体端子连接，并为栅极和主体端子提供开路。

9. 发明申请

US20140097434A1 BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS 有权
标题翻译：后端金属氧化物半导体变送器
公开(公告)号：US20140097434A1
公开(公告)日：2014-04-10
申请号：US13644918
申请日：2012-10-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/775 , G06F17/50 , H01L21/336
CPC分类号： H01L29/93 , H01L27/0688 , H01L27/0808
摘要： Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.
摘要翻译：变容二极管的器件结构，设计结构和制造方法。器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。半导体本体由非晶态或多晶态的含硅半导体材料构成。器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

10. 发明授权

US10811528B2 Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs 有权
公开(公告)号：US10811528B2
公开(公告)日：2020-10-20
申请号：US15927962
申请日：2018-03-21
申请人： International Business Machines Corporation
发明人： Mona Ebrish , Xuefeng Liu , Brent Anderson , Huiming Bu , Junli Wang
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/66
摘要： High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.

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