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1. 发明授权

US09299458B1 Voltage comparator circuit and usage thereof 有权
标题翻译：电压比较器电路及其用途
公开(公告)号：US09299458B1
公开(公告)日：2016-03-29
申请号：US14863011
申请日：2015-09-23
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Lidar Herooti , Noam Jungmann , Elazar Kachir , Donald W. Plass , Hezi Shalom , Israel Wagner
IPC分类号： G11C5/14 , G11C29/50
CPC分类号： G11C29/50 , G11C5/14 , G11C5/145 , G11C11/406 , G11C11/417 , G11C29/021 , G11C29/06 , G11C29/12005 , G11C2029/5004 , G11C2211/4067
摘要： A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold. The method further comprises that in response to said connecting, the supply selector of the circuit is invoked and disconnects one power supply from the memory element; whereby stress testing the circuit, the stress testing tests the memory element without a voltage difference condition, the stress testing tests the another element with the voltage difference condition.
摘要翻译：一种用于测试包括存储元件，电压比较器和电源选择器的电路的方法，所述电路被配置为连接到两个电源，所述电压比较器被配置为提供指示所述两个电源之间的电压差的输出电源选择器被配置为响应于来自电压比较器的输出而选择向存储器元件供电的电源。该方法包括将两个电源连接到电路，其中所述连接包括使两个电源驱动电力到存储器元件和电路的另一元件，其中两个电源之间的电压不同于预定阈值。该方法还包括响应于所述连接，调用电路的供电选择器并从存储元件断开一个电源; 由此对电路进行应力测试，应力测试在没有电压差条件的情况下对存储元件进行测试，应力测试用电压差条件测试另一个元件。

2. 发明授权

US09263096B1 Voltage comparator circuit and usage thereof 有权
标题翻译：电压比较器电路及其用途
公开(公告)号：US09263096B1
公开(公告)日：2016-02-16
申请号：US14476886
申请日：2014-09-04
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Lidar Herooti , Noam Jungmann , Elazar Kachir , Donald W. Plass , Hezi Shalom , Israel Wagner
IPC分类号： G11C7/02 , G11C5/14 , G11C11/419 , G11C29/50 , G11C11/406 , G11C11/417
CPC分类号： G11C29/50 , G11C5/14 , G11C5/145 , G11C11/406 , G11C11/417 , G11C29/021 , G11C29/06 , G11C29/12005 , G11C2029/5004 , G11C2211/4067
摘要： A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.
摘要翻译：一种电路，包括具有第一电压的第一电源和具有第二电压的第二电源，其中所述第一和第二电压至少在所述电路的一些周期中不同，存储元件，其中所述第一和第二电源是驱动到所述存储元件中的电压比较器，连接到所述第一和第二电源的电压比较器，其中所述电压比较器是被配置为在所述第一和第二电源之间的预定阈值上提供指示电压差的数字输出的模数转换器以及电源选择器元件，其中所述电源选择器元件被配置为响应于所述电压比较器的数字输出而从所述存储器元件断开所述第二电源。

3. 发明申请

US20150003147A1 SRAM RESTORE TRACKING CIRCUIT AND METHOD 有权
标题翻译： SRAM恢复跟踪电路和方法
公开(公告)号：US20150003147A1
公开(公告)日：2015-01-01
申请号：US13928949
申请日：2013-06-27
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Noam Jungmann , Elazar Kachir , Donald W. Plass
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/227
摘要： novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1) the wordline (WL) delay and (2) the SRAM cell delay. These two stages are usually the most sensitive for process variation in the memory access path. The restore tracking circuit incorporates two novel topologies for enhanced tracking to SRAM cell behavior. The first topology is a circuit that functions to mimic the wordline load and delay characteristics. The WL stage is very sensitive to process variation due to the large load it must drive and the usually relatively poor slope (i.e. depending on the number of cells the WL). The second topology is a circuit that mimics the SRAM cell load and delay characteristics. The SRAM cell is very sensitive to process variation due to its very small device features and the high number of cells in the memory array.
摘要翻译：新颖有用的SRAM恢复跟踪电路适用于改善不同PVT角的SRAM单元行为的跟踪。 SRAM阵列访问路径主要受两个阶段的影响：（1）字线（WL）延迟和（2）SRAM单元延迟。这两个阶段通常对存储器访问路径中的过程变化最敏感。恢复跟踪电路结合了两种新颖的拓扑，用于增强对SRAM单元行为的跟踪。第一种拓扑结构是用于模拟字线负载和延迟特性的电路。 WL级由于其必须驱动的大负载和通常相对较差的斜率（即取决于WL的单元数量），对工艺变化非常敏感。第二种拓扑结构是模拟SRAM单元负载和延迟特性的电路。 SRAM单元由于其非常小的器件特性和存储器阵列中的大量单元而对工艺变化非常敏感。

4. 发明授权

US11782777B1 Preventing extraneous messages when exiting core recovery 有权
公开(公告)号：US11782777B1
公开(公告)日：2023-10-10
申请号：US17808119
申请日：2022-06-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Gregory William Alexander , Deanna Postles Dunn Berger , Timothy Bronson , Lior Binyamini , Richard Joseph Branciforte , Guy G. Tracy
IPC分类号： G06F11/00 , G06F11/07 , G06F11/20 , G06F11/16
CPC分类号： G06F11/0724 , G06F11/0757 , G06F11/202 , G06F11/1608
摘要： A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

5. 发明申请

US20160071617A1 VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF 有权
标题翻译：电压比较器电路及其使用
公开(公告)号：US20160071617A1
公开(公告)日：2016-03-10
申请号：US14863011
申请日：2015-09-23
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Lidar Herooti , Noam Jungmann , Elazar Kachir , Donald W. Plass , Hezi Shalom , Israel Wagner
IPC分类号： G11C29/50 , G11C5/14
CPC分类号： G11C29/50 , G11C5/14 , G11C5/145 , G11C11/406 , G11C11/417 , G11C29/021 , G11C29/06 , G11C29/12005 , G11C2029/5004 , G11C2211/4067
摘要： A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold. The method further comprises that in response to said connecting, the supply selector of the circuit is invoked and disconnects one power supply from the memory element; whereby stress testing the circuit, the stress testing tests the memory element without a voltage difference condition, the stress testing tests the another element with the voltage difference condition.
摘要翻译：一种用于测试包括存储元件，电压比较器和电源选择器的电路的方法，所述电路被配置为连接到两个电源，所述电压比较器被配置为提供指示所述两个电源之间的电压差的输出电源选择器被配置为响应于来自电压比较器的输出而选择向存储器元件供电的电源。该方法包括将两个电源连接到电路，其中所述连接包括使两个电源驱动电力到存储器元件和电路的另一元件，其中两个电源之间的电压不同于预定阈值。该方法还包括响应于所述连接，调用电路的供电选择器并从存储元件断开一个电源; 由此对电路进行应力测试，应力测试在没有电压差条件的情况下对存储元件进行测试，应力测试用电压差条件测试另一个元件。

6. 发明授权

US09099200B2 SRAM restore tracking circuit and method 有权
标题翻译： SRAM恢复跟踪电路和方法
公开(公告)号：US09099200B2
公开(公告)日：2015-08-04
申请号：US13928949
申请日：2013-06-27
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Noam Jungmann , Elazar Kachir , Donald W. Plass
IPC分类号： G11C11/00 , G11C11/419 , G11C7/22
CPC分类号： G11C11/419 , G11C7/227
摘要： A novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1) the wordline (WL) delay and (2) the SRAM cell delay. These two stages are usually the most sensitive for process variation in the memory access path. The restore tracking circuit incorporates two novel topologies for enhanced tracking to SRAM cell behavior. The first topology is a circuit that functions to mimic the wordline load and delay characteristics. The WL stage is very sensitive to process variation due to the large load it must drive and the usually relatively poor slope (i.e. depending on the number of cells the WL). The second topology is a circuit that mimics the SRAM cell load and delay characteristics. The SRAM cell is very sensitive to process variation due to its very small device features and the high number of cells in the memory array.
摘要翻译：一种新颖有用的SRAM恢复跟踪电路，适用于改善不同PVT角的SRAM单元行为的跟踪。 SRAM阵列访问路径主要受两个阶段的影响：（1）字线（WL）延迟和（2）SRAM单元延迟。这两个阶段通常对存储器访问路径中的过程变化最敏感。恢复跟踪电路结合了两种新颖的拓扑，用于增强对SRAM单元行为的跟踪。第一种拓扑结构是用于模拟字线负载和延迟特性的电路。 WL级由于其必须驱动的大负载和通常相对较差的斜率（即取决于WL的单元数量），对工艺变化非常敏感。第二种拓扑结构是模拟SRAM单元负载和延迟特性的电路。 SRAM单元由于其非常小的器件特性和存储器阵列中的大量单元而对工艺变化非常敏感。

7. 发明授权

US11907724B2 In-memory trace with overlapping processing and logout 有权
公开(公告)号：US11907724B2
公开(公告)日：2024-02-20
申请号：US17592686
申请日：2022-02-04
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Chung-Lung K. Shum , Ludmila Zernakov , Markus Kaltenbach , Jang-Soo Lee
IPC分类号： G06F9/44 , G06F9/38 , G06F11/34
CPC分类号： G06F9/3867 , G06F11/3466
摘要： A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.

8. 发明公开

US20230251864A1 IN-MEMORY TRACE WITH OVERLAPPING PROCESSING AND LOGOUT 审中-公开
公开(公告)号：US20230251864A1
公开(公告)日：2023-08-10
申请号：US17592686
申请日：2022-02-04
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Chung-Lung K. Shum , Ludmila Zernakov , Markus Kaltenbach , Jang-Soo Lee
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3802
摘要： A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.

9. 发明授权

US09715944B1 Automatic built-in self test for memory arrays 有权
公开(公告)号：US09715944B1
公开(公告)日：2017-07-25
申请号：US15183239
申请日：2016-06-15
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Stefan Payer , Wolfgang Penth , Ido Rozenberg
IPC分类号： G11C29/44 , G11C11/419 , G11C29/12 , G06F11/10 , G11C29/54
CPC分类号： G11C29/44 , G06F11/106 , G11C11/419 , G11C29/12 , G11C29/24 , G11C29/54 , G11C2029/4402
摘要： A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0≦i≦n−1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.

10. 发明申请

US20160071551A1 VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF 有权
标题翻译：电压比较器电路及其使用
公开(公告)号：US20160071551A1
公开(公告)日：2016-03-10
申请号：US14476886
申请日：2014-09-04
申请人： International Business Machines Corporation
发明人： Lior Binyamini , Lidar Herooti , Noam Jungmann , Elazar Kachir , Donald W. Plass , Hezi Shalom , Israel Wagner
IPC分类号： G11C5/14 , G11C29/50 , G11C11/419
CPC分类号： G11C29/50 , G11C5/14 , G11C5/145 , G11C11/406 , G11C11/417 , G11C29/021 , G11C29/06 , G11C29/12005 , G11C2029/5004 , G11C2211/4067
摘要： A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.
摘要翻译：一种电路，包括具有第一电压的第一电源和具有第二电压的第二电源，其中所述第一和第二电压至少在所述电路的一些周期中不同，存储元件，其中所述第一和第二电源是驱动到所述存储元件中的电压比较器，连接到所述第一和第二电源的电压比较器，其中所述电压比较器是被配置为在所述第一和第二电源之间的预定阈值上提供指示电压差的数字输出的模数转换器以及电源选择器元件，其中所述电源选择器元件被配置为响应于所述电压比较器的数字输出而从所述存储器元件断开所述第二电源。

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