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1. 发明申请

WO2018125232A1 DPLL WITH ADJUSTABLE DELAY IN INTEGER OPERATION MODE 审中-公开
公开(公告)号：WO2018125232A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069584
申请日：2016-12-30
申请人： INTEL IP CORPORATION , DGANI, Yair , KERNER, Michael , BANIN, Elan , DINUR, Nati , GIL, Horovitz , ROTEM, Banin
发明人： DGANI, Yair , KERNER, Michael , BANIN, Elan , DINUR, Nati , GIL, Horovitz , ROTEM, Banin
IPC分类号： H04L7/033 , H04L7/00 , H03L7/08
摘要： Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

2. 发明申请

WO2012134676A2 TIME DOMAIN SIGNAL GENERATION 审中-公开
标题翻译：时域信号发生
公开(公告)号：WO2012134676A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/026347
申请日：2012-02-23
申请人： INTEL CORPORATION , KERNER, Michael , KRAVTSOV, Vladimir , HAREL, Tom
发明人： KERNER, Michael , KRAVTSOV, Vladimir , HAREL, Tom
IPC分类号： H04J11/00 , H04B7/26
CPC分类号： H04L27/2613 , H03H17/0213 , H03H17/0264 , H03H17/0657 , H03H17/0685 , H03H2017/0214 , H04L27/2633 , H04L27/2634 , H04L27/264
摘要： Embodiments of apparatuses, articles, methods, and systems for efficient generation of a time domain signal in multi-carrier communications are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里总体上描述了用于在多载波通信中高效生成时域信号的装置，物品，方法和系统的实施例。其他实施例可以被描述和要求保护。

3. 发明申请

WO2017111882A1 COMMUNICATION DEVICE AND METHOD FOR PERFORMING RADIO COMMUNICATION 审中-公开
标题翻译：通信设备和用于执行无线电通信的方法
公开(公告)号：WO2017111882A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/066969
申请日：2015-12-21
申请人： INTEL IP CORPORATION
发明人： ALMOG, Itay , KERNER, Michael
IPC分类号： H04L27/00 , H04L25/02 , H04L1/00
CPC分类号： H04L1/00 , H04L25/02 , H04L27/3411 , H04L27/366
摘要： A communication device is provided that includes a modulation circuit configured to modulate a signal comprising a first signal portion of a first data type and a second signal portion of a second data type. The modulation circuit is configured to modulate the first signal portion in accordance with a first modulation scheme and the second signal portion in accordance with a second modulation scheme. At least one of the first data type is different from the second data type or the second modulation scheme is different from the first modulation scheme. The communication device further includes a modification circuit configured to modify the modulated first signal portion based on a first modification scheme and the second signal portion based on a second modification scheme. The communication device further includes a transmitter configured to transmit the modified first signal portion and the modified second signal portion.
摘要翻译：提供了一种通信设备，该通信设备包括调制电路，该调制电路被配置为调制包括第一数据类型的第一信号部分和第二数据类型的第二信号部分的信号。调制电路被配置为根据第一调制方案调制第一信号部分，并根据第二调制方案调制第二信号部分。第一数据类型中的至少一个不同于第二数据类型，或者第二调制方案不同于第一调制方案。该通信设备还包括修改电路，该修改电路被配置为基于第一修改方案修改调制后的第一信号部分，并基于第二修改方案修改第二信号部分。该通信设备还包括发射机，该发射机被配置为发送修改的第一信号部分和修改的第二信号部分。

4. 发明申请

WO2018158614A1 TIME-TO-DIGITAL CONVERTER, DIGITAL PHASE-LOCKED LOOP, METHOD FOR OPERATING A TIME-TO-DIGITAL CONVERTER, AND METHOD FOR A DIGITAL PHASE-LOCKED LOOP 审中-公开
公开(公告)号：WO2018158614A1
公开(公告)日：2018-09-07
申请号：PCT/IB2017/051221
申请日：2017-03-02
申请人： INTEL IP CORPORATION
发明人： DGANI, Yair , KERNER, Michael , BANIN, Elan , SHUMAKER, Evgeny , HOROVITZ, Gil , DEGANI, Ofir , BANIN, Rotem , FARBER, Aryeh , AVIVI, Rotem , GORDON, Eshel , SELA, Tami
IPC分类号： G04F10/00 , H03L7/081
摘要： A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

5. 发明申请

WO2018118226A1 DIGITAL POLAR TRANSMITTER HAVING A DIGITAL FRONT END 审中-公开
公开(公告)号：WO2018118226A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/059195
申请日：2017-10-31
申请人： INTEL IP CORPORATION
发明人： PARKER, Uri , BANIN, Elan , KERNER, Michael , DEGANI, Ofir
IPC分类号： H04L27/26 , H04L27/36 , H04B1/04
CPC分类号： H04B1/02 , G11B20/10055 , G11B20/1024 , H02M1/12 , H02P27/08 , H04B1/04 , H04L27/361
摘要： A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal relative to a carrier frequency at a carrier frequency related sample rate, calculate zero crossing positions of the resampled signal, generate delay to time converter (DTC) commands based on the zero crossing positions, calculate amplitude values for the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the amplitude values. The transmit chain is configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.

6. 发明申请

WO2018063661A1 DEVICE AND METHOD TO REDUCE POWER AMPLIFIER POWER CONSUMPTION 审中-公开
标题翻译：降低功率放大器功率消耗的装置和方法
公开(公告)号：WO2018063661A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049053
申请日：2017-08-29
申请人： INTEL IP CORPORATION
发明人： KERNER, Michael , PERLMUTTER, Uri , FRIEDMAN, Avishay , BANIN, Rotem , MAIMON, Tzvi
IPC分类号： H04L27/26 , H04L5/00
摘要： A wireless device and method of power consumption reduction are generally described herein. The wireless device may map a plurality of data symbols to sub-carriers for an orthogonal frequency division multiplexing (OFDM) transmission. The wireless device may divide the plurality of data symbols into first and second groups of data symbols. The wireless device may generate a first OFDM signal from the first group of data symbols for amplification by a first power amplifier (PA). The wireless device may generate a second OFDM signal from the second group of data symbols for amplification by a second PA. The data symbols of the first and second groups may be selected to provide a PAPR of the first OFDM signal that is lower than a PAPR of a composite OFDM signal based on the plurality of data symbols.
摘要翻译：本文中一般描述了无线设备和降低功耗的方法。无线设备可以将多个数据符号映射到副载波以用于正交频分复用（OFDM）传输。无线设备可以将多个数据符号分成第一和第二组数据符号。无线设备可以从第一组数据符号生成第一OFDM信号以供第一功率放大器（PA）放大。无线设备可以从第二组数据符号生成第二OFDM信号以供第二PA放大。可以选择第一和第二组的数据符号以提供第一OFDM信号的PAPR，其低于基于多个数据符号的复合OFDM信号的PAPR。

7. 发明申请

WO2019190469A1 TRANSMITTERS AND METHODS FOR OPERATING THE SAME 审中-公开
公开(公告)号：WO2019190469A1
公开(公告)日：2019-10-03
申请号：PCT/US2018/024455
申请日：2018-03-27
申请人： INTEL IP CORPORATION
发明人： BELITZER, Alexander , YOFFE, Yaron , COHEN, Yaniv , KERNER, Michael
IPC分类号： H04B1/62 , H04B1/66
摘要： A transmitter is provided. The transmitter includes an envelope tracking circuit, wherein the envelope tracking circuit includes an envelope circuit configured to generate, based on a baseband signal, an envelope signal indicating a temporal course of the baseband signal's envelope. Further, the envelope tracking circuit includes a bandwidth reduction circuit configured to generate a bandwidth reduced envelope signal based on the envelope signal, and a DC-to- DC converter configured to generate a supply voltage for a power amplifier of the transmitter based on the bandwidth reduced envelope signal. The transmitter additionally includes a predistortion circuit configured to generate a predistorted baseband signal based on the baseband signal and an adjustable predistortion configuration. The predistortion circuit is further configured to adjust the predistortion configuration based on the bandwidth reduced envelope signal.

8. 发明申请

WO2018160312A1 SPUR CANCELATION USING INVERSE SPUR INJECTION 审中-公开
公开(公告)号：WO2018160312A1
公开(公告)日：2018-09-07
申请号：PCT/US2018/016140
申请日：2018-01-31
申请人： INTEL IP CORPORATION
发明人： AVIVI, Rotem , KERNER, Michael , GUREVITZ, Assaf
IPC分类号： H04B1/525 , H04B1/04
摘要： A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.

9. 发明申请

WO2018057195A1 ZERO-CROSS-PRE-DISTORTION (ZCPD) ALGORITHM FOR DTC BASED POLAR DTX 审中-公开
标题翻译：基于DTC的极化DTX零交叉预失真（ZCPD）算法
公开(公告)号：WO2018057195A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/047954
申请日：2017-08-22
申请人： INTEL IP CORPORATION
发明人： BANIN, Elan , PARKER, Uri , DEGANI, Ofir , KERNER, Michael
IPC分类号： H04L25/06
CPC分类号： H04B1/0475 , H04B2001/0425 , H04L27/367
摘要： Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
摘要翻译：通常描述补偿带通滤波器的设备和方法。 DTx包括产生输出信号的BPF和具有过零（ZC）预失真器（ZCP）的DFE。 ZCPD补偿由BPF引起的期望模拟信号的ZC失真。 ZCPD调整DTC代码字以生成要应用于BPF的DTx输出信号。补偿取决于紧接在ZC之前和之后的方波的幅度。补偿后的DTC和DPA码字用于生成DTx输出信号。 ZCPD产生的补偿对于DTC和DPA码字的非线性响应没有补偿。

10. 发明申请

WO2017153853A1 APPARATUSES AND METHODS FOR COMPENSATING PHASE FLUCTUATIONS 审中-公开
标题翻译：补偿相位波动的装置和方法
公开(公告)号：WO2017153853A1
公开(公告)日：2017-09-14
申请号：PCT/IB2017/050409
申请日：2017-01-26
申请人： INTEL IP CORPORATION
发明人： PERLMUTTER, Uri , KERNER, Michael , PARKER, Uri
IPC分类号： H04L7/033 , H04L7/00
摘要： The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).
摘要翻译：本公开涉及用于补偿载波或时钟信号相位波动的方法和装置。一种装置包括数字锁相环（210），该数字锁相环包括用于由数字锁相环生成的参考信号（218）和输出信号（212）之间的相位误差（216）的相位误差输出（214）相位旋转器（220），耦合到相位误差输出（214）并且被配置为基于相位误差（216）旋转数据信号的相位。

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