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1. 发明申请

WO2016099462A1 WEARABLE COMPUTING DEVICE 审中-公开
标题翻译：可擦写计算设备
公开(公告)号：WO2016099462A1
公开(公告)日：2016-06-23
申请号：PCT/US2014/070632
申请日：2014-12-16
申请人： INTEL CORPORATION
发明人： ALBERS, Sven , REINGRUBER, Klaus , OSSIANDER, Teodora , WOLTER, Andreas , KOLLER, Sonja , SEIDEMANN, Georg , PROSCHWITZ, Jan , BARTH, Hans-Joachim , ELSHOF, Bastiaan
IPC分类号： G06F3/01
CPC分类号： G06F3/044 , G01L1/24 , G06F1/163 , G06F3/03547 , G06F3/038 , G06F3/042 , G06F3/045 , G06F2203/04102 , G06F2203/04109 , H04B1/385
摘要： Some forms relate to wearable computing devices that include a "touch pad" like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.
摘要翻译：一些形式涉及包括诸如接口的“触摸板”的可穿戴计算设备。在一些形式中，可穿戴式计算设备的示例可以与（或附着）纺织品（即服装）集成。在其他形式中，可穿戴式计算设备的示例可以直接附接到使用任何示例性可穿戴计算设备的某人的皮肤（即类似于绷带）。示例性可穿戴计算设备包括柔性触摸板，其可以允许可穿戴计算设备的用户更容易地操作可穿戴式计算设备。本文所述的示例性可穿戴计算设备可以包括各种电子设备。一些示例包括电源和/或其他类型的电子设备中的通信设备。

2. 发明申请

WO2022271241A1 MICROELECTRONIC ASSEMBLIES HAVING TOPSIDE POWER DELIVERY STRUCTURES 审中-公开
公开(公告)号：WO2022271241A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/021880
申请日：2022-03-25
申请人： INTEL CORPORATION
发明人： WAIDHAS, Bernd , HANNA, Carlton , MOREIN, Stephen , KESER, Lizbeth , SEIDEMANN, Georg
IPC分类号： H01L25/065 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/18 , H01L23/36 , H01L2224/0557 , H01L2224/06181 , H01L2224/08225 , H01L2224/24137 , H01L23/3675 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/24 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L2924/19041 , H01L2924/19042 , H01L2924/19106 , H05K1/181
摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

3. 发明申请

WO2018004930A1 INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A CHIP RECESS 审中-公开
标题翻译：集成电路封装组件，包括芯片存储器
公开(公告)号：WO2018004930A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035047
申请日：2017-05-30
申请人： INTEL CORPORATION
发明人： SEIDEMANN, Georg , REINGRUBER, Klaus
IPC分类号： H01L25/07 , H01L23/28 , H01L21/56 , H01L23/522
摘要： IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
摘要翻译： IC封装组件包括其中IC芯片表面相对于模制化合物凹陷的模塑料。在模制过程中，IC芯片的厚度可以相对于其厚度减小。然后，另一个IC芯片，散热器等可以占据由模制化合物框起的合成凹陷以实现精细的堆叠间距。在一些实施例中，层叠封装（PoP）组件包括倒装芯片键合到第一封装衬底的中心模制IC芯片。然后将第二IC芯片倒装芯片接合到的第二衬底通过贯通模制通孔电耦合到第一衬底。在PoP组件内，第二IC芯片可以与中心模制的IC芯片背靠背地布置，以便占据由模塑料构成的凹陷。

4. 发明申请

WO2015137936A1 MICROELECTRONIC PACKAGE HAVING A PASSIVE MICROELECTRONIC DEVICE DISPOSED WITHIN A PACKAGE BODY 审中-公开
标题翻译：具有在包装体内处理的被动微电子器件的微电子封装
公开(公告)号：WO2015137936A1
公开(公告)日：2015-09-17
申请号：PCT/US2014/024112
申请日：2014-03-12
申请人： INTEL CORPORATION , MEYER, Thorsten , OFNER, Gerald , WOLTER, Andreas , SEIDEMANN, Georg , ALBERS, Sven , GEISSLER, Christian
发明人： MEYER, Thorsten , OFNER, Gerald , WOLTER, Andreas , SEIDEMANN, Georg , ALBERS, Sven , GEISSLER, Christian
IPC分类号： H01L23/12
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L23/49822 , H01L23/50 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/16 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/24195 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/15151 , H01L2924/15159 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105
摘要： A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
摘要翻译：一种微电子封装，包括设置在封装主体内的无源微电子器件，其中所述封装体是所述微电子封装的对所述微电子封装提供支撑和/或刚度的部分。在倒装芯片型微电子封装中，封装主体可以包括微电子衬底，活性微电子器件电连接到微电子衬底。在嵌入式设备型微电子封装中，封装体可以包括其中嵌入有源微电子器件的材料。

5. 发明申请

WO2015088486A1 ANTENNA ON CERAMICS FOR A PACKAGED DIE 审中-公开
标题翻译：用于包装的陶瓷的天线
公开(公告)号：WO2015088486A1
公开(公告)日：2015-06-18
申请号：PCT/US2013/073950
申请日：2013-12-09
申请人： INTEL CORPORATION , WOLTER, Andreas , MARUTHAMUTHU, Saravana , KNUDSEN, Mikael , MEYER, Thorsten , SEIDEMANN, Georg , HERRERO, Pablo , JAERVINEN, Pauli
发明人： WOLTER, Andreas , MARUTHAMUTHU, Saravana , KNUDSEN, Mikael , MEYER, Thorsten , SEIDEMANN, Georg , HERRERO, Pablo , JAERVINEN, Pauli
IPC分类号： H01L23/66
CPC分类号： H01L23/66 , H01L21/4846 , H01L23/295 , H01L23/3128 , H01L23/481 , H01L23/49833 , H01L23/49838 , H01L23/552 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2223/6616 , H01L2223/6677 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/2919 , H01L2224/32225 , H01L2224/73253 , H01L2224/73267 , H01L2225/06517 , H01L2225/06548 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1421 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01Q1/38 , H01Q1/50 , H01Q1/526 , H01L2924/00
摘要： An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.
摘要翻译：在可用于封装模具的陶瓷上描述天线。在一个示例中，封装具有管芯，管芯上的陶瓷衬底，附着到陶瓷衬底的天线以及将天线电连接到管芯的导电引线。

7. 发明公开

EP4199013A1 SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DIE AND METHOD FOR FORMING A SEMICONDUCTOR PACKAGE OR A SEMICONDUCTOR DIE 审中-实审
公开(公告)号：EP4199013A1
公开(公告)日：2023-06-21
申请号：EP22213196.3
申请日：2022-12-13
申请人： INTEL Corporation
发明人： MOLZER, Wolfgang , GOSSNER, Harald , SEIDEMANN, Georg , WAIDHAS, Bernd , LANGENBUCH, Michael
IPC分类号： H01F27/28 , H01F41/04 , H01L23/522 , H01F17/00
摘要： A semiconductor package comprises a semiconductor die and a wiring structure, which is electrically connected to the semiconductor die. Further, the semiconductor package comprises a magnetic material. The magnetic material embeds and/or encircles a portion of the wiring structure.

8. 发明公开

EP4020532A2 ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES 审中-实审
公开(公告)号：EP4020532A2
公开(公告)日：2022-06-29
申请号：EP21196293.1
申请日：2021-09-13
申请人： Intel Corporation
发明人： WAIDHAS, Bernd , WOLTER, Andreas , SEIDEMANN, Georg , WAGNER, Thomas
IPC分类号： H01L21/60 , H01L25/065
摘要： Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer (121) and a first die (125A) embedded in the mold layer. In an embodiment, the first die comprises first pads (P1) at a first pitch and second pads (P2) at a second pitch. In an embodiment, the electronic package further comprises a second die (125B) embedded in the mold layer, where the second die comprises third pads (P3) at the first pitch and fourth pads (P4) at the second pitch. In an embodiment, a bridge die (127) is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

9. 发明公开

EP4254492A1 DUAL-SIDED TERMINAL DEVICE WITH SPLIT SIGNAL AND POWER ROUTING 审中-实审
公开(公告)号：EP4254492A1
公开(公告)日：2023-10-04
申请号：EP23153060.1
申请日：2023-01-24
申请人： Intel Corporation
发明人： WAIDHAS, Bernd , SEIDEMANN, Georg , PROSCHWITZ, Jan , REIF, Stefan , PRASAD, Vishnu
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522 , H01L23/498
摘要： A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.

10. 发明公开

EP4156257A2 SEMICONDUCTOR DIES AND DEVICES WITH A COIL FOR INDUCTIVE COUPLING 审中-实审
公开(公告)号：EP4156257A2
公开(公告)日：2023-03-29
申请号：EP22197159.1
申请日：2022-09-22
申请人： INTEL Corporation
发明人： OSTERMAYR, Martin , LUTZ, Walther , ASSENMACHER, Joachim , SEIDEMANN, Georg
IPC分类号： H01L23/522 , H01L27/06
摘要： A semiconductor die is disclosed, including circuitry comprising a transistor at a frontside of a semiconductor substrate, and a backside inductor at a backside of the semiconductor substrate. The backside inductor is electrically connected to the transistor of the circuitry.

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