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1. 发明申请

WO2017112249A1 HARDWARE CONTENT-ASSOCIATIVE DATA STRUCTURE FOR ACCELERATION OF SET OPERATIONS 审中-公开
标题翻译：加速集合运算的硬件内容关联数据结构
公开(公告)号：WO2017112249A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063306
申请日：2016-11-22
申请人： INTEL CORPORATION
发明人： ANDERSON, Michael J. , LI, Sheng R. , PARK, Jong Soo , PATWARY, Md Mostofa Ali , SATISH, Nadathur Rajagopalan , SMELYANSKIY, Mikhail , SUNDARAM, Narayanan
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30018 , G06F9/30021 , G06F9/3005 , G06F9/3877 , G06F12/0875 , G06F17/10 , G06F17/30 , G06F2212/452
摘要： A processor includes a front end to receive an instruction, a decoder to decode the instruction, a set operations logic unit (SOLU) to execute the instruction, and a retirement unit. The SOLU includes logic to store a first set of key-value pairs in a content-associative data structure, to receive a second set of key-value pairs, and to identify key-value pairs in the two sets with matching keys. The SOLU includes logic to add the second set of key-value pairs to the first set to produce an output set, and to apply an operation to the values of key-value pairs with matching keys, generating a single value for the matching key. The SOLU includes logic to produce an output set that includes key-value pairs from the first set with matching keys, and to discard key-value pairs from the first set with unique keys.
摘要翻译：处理器包括用于接收指令的前端，用于对指令进行解码的解码器，用于执行指令的置位操作逻辑单元（SOLU）以及引退单元。 SOLU包括用于将第一组键值对存储在内容关联数据结构中，接收第二组键值对并且用匹配键来识别两组中的键值对的逻辑。 SOLU包括将第二组键值对添加到第一组以产生输出集的逻辑，并且将操作应用于具有匹配键的键值对的值，从而为匹配键生成单个值。 SOLU包含的逻辑可以生成一个输出集合，该集合包含第一个集合中具有匹配键的键值对，并使用唯一键丢弃第一个集合中的键值对。

2. 发明申请

WO2017112182A1 APPARATUS AND METHOD FOR ACCELERATING GRAPH ANALYTICS 审中-公开
标题翻译：用于加速图解分析的装置和方法
公开(公告)号：WO2017112182A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062784
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： ANDERSON, Michael , LI, Sheng , PARK, Jong Soo , PATWARY, Md Mostofa Ali , SATISH, Nadathur Rajagopalan , SMELYANSKIY, Mikhail , SUNDARAM, Narayanan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30192 , G06F9/3802 , G06F12/0811 , G06F12/084 , G06F2212/455
摘要： An apparatus and method are described for accelerating graph analytics. For example, one embodiment of a processor comprises: an instruction fetch unit to fetch program code including set intersection and set union operations; a graph accelerator unit (GAU) to execute at least a first portion of the program code related to the set intersection and set union operations and generate results; and an execution unit to execute at least a second portion of the program code using the results provided from the GAU.
摘要翻译：描述了用于加速图分析的装置和方法。例如，处理器的一个实施例包括：指令获取单元，用于获取包括集合交集和设置联合操作的程序代码; 图形加速器单元（GAU），用于执行与所述集合交集有关的程序代码的至少第一部分并设置联合操作并生成结果; 以及执行单元，用于使用从GAU提供的结果来执行程序代码的至少第二部分。

3. 发明申请

WO2013048413A1 CACHE AND/OR SOCKET SENSITIVE MULTI-PROCESSOR CORES BREADTH-FIRST TRAVERSAL 审中-公开
标题翻译：高速缓存和/或插座敏感多处理器最初的第一个TRAVERSAL
公开(公告)号：WO2013048413A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054016
申请日：2011-09-29
申请人： INTEL CORPORATION , SATISH, Nadathur Rajagopalan , KIM, Changkyu , CHHUGANI, Jatin , SEWALL, Jason D.
发明人： SATISH, Nadathur Rajagopalan , KIM, Changkyu , CHHUGANI, Jatin , SEWALL, Jason D.
IPC分类号： G06F9/38 , G06F9/06 , G06F15/80 , G06F13/14
CPC分类号： G06F9/52
摘要： Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are disclosed. In embodiments, a vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. In embodiments, potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. In various embodiments, the threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed. Other embodiments may be disclosed or claimed.
摘要翻译：公开了通过并行线程与缓存和/或套接字敏感的宽度优先遍历遍历图形的方法，装置和存储装置。在实施例中，可以采用顶点访问阵列（VIS）来跟踪所访问的图形顶点。 VIS可以分为VIS子阵列，考虑到LLC的缓存大小，以减少驱逐的可能性。在实施例中，可以采用潜在边界顶点阵列（PBV）来存储针对当前迭代中被访问的顶点的下一次迭代的潜在边界顶点。为每个线程生成的PBV的数量可以考虑多个套接字，所使用的处理器核在其上分布。在各种实施例中，螺纹可以是负载平衡的; 可以考虑进一步的数据局部性意识以减少套接字间通信，和/或可以采用锁定和无原子的更新操作。可以公开或要求保护其他实施例。

4. 发明申请

WO2017172173A1 INSTRUCTION, CIRCUITS, AND LOGIC FOR GRAPH ANALYTICS ACCELERATION 审中-公开
标题翻译：图形分析加速的指令，电路和逻辑
公开(公告)号：WO2017172173A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019845
申请日：2017-02-28
申请人： INTEL CORPORATION
发明人： WU, Lisa K. , HAM, Tae Jun , SATISH, Nadathur Rajagopalan , SUNDARAM, Narayanan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/5027 , G06F9/3877 , G06F2209/509 , G06T1/20 , Y02D10/22
摘要： A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor.
摘要翻译：处理器包括前端，其包括用于接收和解码指令的电路。该指令是执行图形分析功能并将指令传递给图形加速器。图形加速器包括将图形顶点和图形边缘处理为数据类型的电路，执行指令并将指令结果传递给处理器的存储器子系统。

5. 发明申请

WO2017105708A1 SORTING DATA AND MERGING SORTED DATA IN AN INSTRUCTION SET ARCHITECTURE 审中-公开
标题翻译：在指令集体系结构中排序数据并合并分类数据
公开(公告)号：WO2017105708A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061901
申请日：2016-11-14
申请人： INTEL CORPORATION
发明人： MISHRA, Asit K. , MARR, Deborah T. , PARK, Jong Soo , SATISH, Nadathur Rajagopalan , SMELYANSKIY, Mikhail , ANDERSON, Michael , PATWARY, Mostofa Ali , SUNDARAM, Narayanan , LI, Sheng
IPC分类号： G06F9/38
CPC分类号： G06F9/30192 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145
摘要： A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.
摘要翻译：处理装置包括分类模块，其将多个元素中的每一个添加到寄存器静止中的对应位置的位置值，从而导致在相应位置中的多个变换元素。多个元素包括多个比特。排序模块将多个变换元素中的每一个与自身和彼此进行比较。排序模块还基于比较将多个变换元素中的每一个分配启用或禁用指示符中的一个。排序模块还对分配给多个变换元素中的每一个的启用指示符的数量进行计数，以生成多个元素的排序序列。

6. 发明申请

WO2013147880A1 METHOD AND APPARATUS OF INSTRUCTION THAT MERGES AND SORTS SMALLER SORTED VECTORS INTO LARGER SORTED VECTOR 审中-公开
标题翻译：方法和装置的装配和排队较小的载体到较大的载体矢量
公开(公告)号：WO2013147880A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031645
申请日：2012-03-30
申请人： INTEL CORPORATION , CHHUGANI, Jatin , CK KIM, Changkyu , SATISH, Nadathur Rajagopalan
发明人： CHHUGANI, Jatin , CK KIM, Changkyu , SATISH, Nadathur Rajagopalan
IPC分类号： G06F1/00 , G06F9/22 , G06F9/30
CPC分类号： G06F7/36 , G06F7/32 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3005 , G06F9/3012 , G06F9/3867
摘要： A semiconductor chip is described that includes an instruction execution unit having a functional unit, said functional unit having minimum and maximum comparison circuitry followed by interleaving circuitry, said minimum and maximum comparison circuitry to respectively identify minimums and maximums of same positioned elements from two different sets of sorted elements, said interleaving circuitry to interleave said minimums and maximums to help form a third sorted set composed of elements from said different sets and being larger than each of said different sets.
摘要翻译：描述了一种半导体芯片，其包括具有功能单元的指令执行单元，所述功能单元具有跟随交织电路的最小和最大比较电路，所述最小和最大比较电路分别从两个不同的集合确定相同定位元件的最小值和最大值所述交织电路交织所述最小值和最大值以帮助形成由所述不同集合的元素组成的第三排序集合，并且大于所述不同集合中的每一个。

7. 发明申请

WO2013032436A1 PARALLEL OPERATION ON B+ TREES 审中-公开
标题翻译：平行操作在B + TREES
公开(公告)号：WO2013032436A1
公开(公告)日：2013-03-07
申请号：PCT/US2011/049569
申请日：2011-08-29
申请人： INTEL CORPORATION , SEWALL, Jason D. , KIM, Changkya , CHHUGANI, Jatin , SATISH, Nadathur Rajagopalan
发明人： SEWALL, Jason D. , KIM, Changkya , CHHUGANI, Jatin , SATISH, Nadathur Rajagopalan
IPC分类号： G06F9/38 , G06F9/06
CPC分类号： G06F17/30327 , G06F9/5005 , G06F2209/5018
摘要： Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and redistribution may include a set of threads executing a batch of B+ tree operations on a B+ tree in parallel. The batch of operations may be partitioned amongst the threads. Next, a search may be performed to determine which leaf nodes in the B+ tree are to be affected by which operations. Then, the threads may redistribute operations between each other such that multiple threads will not operate on the same leaf node. The threads may then perform B+ tree operations on the leaf nodes of the B+ tree in parallel. Subsequent modifications to nodes in the B+ may similarly be redistributed and performed in parallel as the threads work up the tree.
摘要翻译：描述了用于B +树的并行处理的技术和系统的实施例。具有分区和再分配的并行B +树处理模块可以包括一组在B +树上并行执行一批B +树操作的线程。该批操作可以在线程之间划分。接下来，可以执行搜索以确定B +树中的哪些叶节点将受哪些操作影响。然后，线程可以在彼此之间重新分配操作，使得多个线程将不在同一叶节点上操作。然后，线程可以并行地在B +树的叶节点上执行B +树操作。当线程处理树时，对B +中的节点的后续修改可以类似地重新分布并且并行执行。

8. 发明公开

EP4006723A2 FAST DATA OPERATIONS AND FINITE STATE MACHINE FOR MACHINE LEARNING 审中-公开
公开(公告)号：EP4006723A2
公开(公告)日：2022-06-01
申请号：EP22152342.6
申请日：2018-03-01
申请人： Intel Corporation
发明人： MA, Liwel , SATISH, Nadathur Rajagopalan , BOTTLESON, Jeremy , AKHBARI, Farshad , NURVITADHI, Eriko , APPU, Abhishek R. , KOKER, Altug , SINHA, Kamal , RAY, Joydeep , VEMBU, Balaji , RANGANATHAN, Vasanth , JAHAGIRDAR, Sanjeev
IPC分类号： G06F9/448 , G06T1/20
摘要： A mechanism is described for facilitating fast data operations for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a compute pipeline of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

9. 发明公开

EP3792839A1 COMPUTE OPTIMIZATION MECHANISM 审中-公开
公开(公告)号：EP3792839A1
公开(公告)日：2021-03-17
申请号：EP20205015.9
申请日：2018-03-02
申请人： INTEL Corporation
发明人： APPU, Abhishek R. , KOKER, Altug , HURD, Linda L. , KIM, Dukhwan , MACPHERSON, Mike B. , WEAST, John C. , CHEN, Feng , AKHBARI, Farshad , SRINIVASA, Narayan , SATISH, Nadathur Rajagopalan , TANG, Ping T. , RAY, Joydeep , STRICKLAND, Michael S. , CHEN, Xiaoming , YAO, Anbang , SHPEISMAN, Tatiana
IPC分类号： G06N3/063 , G06F9/30 , G06F9/38 , G06F9/46 , G06T1/20
摘要： The present disclosure provides an apparatus comprising an interconnect fabric comprising one or more switches, a memory interface coupled to the interconnect fabric, an input/output (10) interface coupled to the interconnect fabric an array of processing clusters coupled to the interconnect fabric, the array of processing clusters to process instructions at variable precisions. At least one processing cluster comprising a plurality of registers to store source operands at variable precisions and an execution unit comprising a plurality of arithmetic logic units (ALUs) to execute one or more of the instructions to perform a mixed-precision fused multiply-accumulate (FMAC) operation of D = A ∗ B + C. Each source operand A, B, and C may be any of FP64, FP32, FP16, INT32, INT16, INT8 or INT4. An ALU is to generate the result operand D by multiplying source operand A with source operand B to generate an intermediate product, and adding the intermediate product to source operand C.

10. 发明公开

EP3396528A1 DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS 审中-公开
公开(公告)号：EP3396528A1
公开(公告)日：2018-10-31
申请号：EP18162625.0
申请日：2018-03-19
申请人： INTEL Corporation
发明人： KOKER, Altug , APPU, Abhishek R. , SINHA, Kamal , RAY, Joydeep , VEMBU, Balaji , OULD-AHMED-VALL, Elmoustapha , BAGHSORKHI, Sara S. , YAO, Anbang , NEALIS, Kevin , CHEN, Xiaoming , WEAST, John C. , GOTTSCHLICH, Justin E. , SURTI, Prasoonkumar , SAKTHIVEL, Chandrasekaran , AKHBARI, Farshad , SATISH, Nadathur Rajagopalan , MA, Liwei , BOTTLESON, Jeremy , NURVITADHI, Eriko , SCHLUESSLER, Travis T. , SHAH, Ankur N. , KENNEDY, Jonathan , RANGANATHAN, Vasanth , JAHAGIRDAR, Sanjeev
IPC分类号： G06F9/28 , G06N3/04 , G06N3/063 , G06F9/50
CPC分类号： G06N3/08 , G06F9/505 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N99/005
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

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