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1. 发明申请

WO2013095556A1 CONFIGURATION OF ACOUSTO-OPTIC DEFLECTORS FOR LASER BEAM SCANNING 审中-公开
标题翻译：用于激光光束扫描的光学反射器的配置
公开(公告)号：WO2013095556A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067001
申请日：2011-12-22
申请人： INTEL CORPORATION , LI, Yonggang , SALAMA, Islam , ZHANG, Chong
发明人： LI, Yonggang , SALAMA, Islam , ZHANG, Chong
IPC分类号： G02B26/10
CPC分类号： G02B26/10 , B23K2201/42 , G02F1/33 , G02F2001/291 , G02F2201/16
摘要： A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second acousto-optic deflector receives the diffracted laser beam. The second acousto-optic deflector diffracts the received diffracted laser beam along a second axis.
摘要翻译：第一声光偏转器接收激光束。第一声光偏转器沿着第一轴衍射接收的激光束。第二声光偏转器接收衍射激光束。第二声光偏转器沿着第二轴衍射所接收的衍射激光束。

2. 发明申请

WO2009032390A2 METHOD OF PROVIDING PATTERNED EMBEDDED CONDUCIVE LAYER USING LASER AIDED ETCHING OF DIELECTRIC BUILD-UP LAYER 审中-公开
标题翻译：使用激光辅助蚀刻构建层提供图案化嵌入的有源层的方法
公开(公告)号：WO2009032390A2
公开(公告)日：2009-03-12
申请号：PCT/US2008/068149
申请日：2008-06-25
申请人： INTEL CORPORATION , LI, Yonggang
发明人： LI, Yonggang
CPC分类号： H05K3/0032 , H05K3/0035 , H05K3/0055 , H05K3/107 , H05K3/465 , H05K2203/0796
摘要： A method of providing a patterned conductive layer. The method includes: providing a build-up layer comprising an insulating material; laser irradiating selected portions of the build-up layer according to a predetermined pattern of the patterned conductive layer to be provided, laser irradiating comprising using a laser beam having a photon energy higher than a bonding energy of at least some of the chemical bonds of the insulating material to yield predetermined laser-weakened portions of the build-up layer according to the predetermined pattern; removing the laser-weakened portions of the build-up layer to yield recesses according to the predetermined pattern; and filling the recesses with a conductive material to yield the patterned conductive layer.
摘要翻译：一种提供图案化导电层的方法。该方法包括：提供包含绝缘材料的积层; 根据待提供的图案化导电层的预定图案，激光照射构建层的选定部分;激光照射包括使用光子能量高于光子能量的至少一些化学键的键能的激光束; 以根据预定图案产生积层的预定激光削弱部分; 根据预定图案去除积聚层的激光削弱部分以产生凹陷; 并用导电材料填充凹槽以产生图案化的导电层。

3. 发明申请

WO2016144320A1 SELECTIVE METALLIZATION OF AN INTEGRATED CIRCUIT (IC) SUBSTRATE 审中-公开
标题翻译：集成电路（IC）基板的选择性金属化
公开(公告)号：WO2016144320A1
公开(公告)日：2016-09-15
申请号：PCT/US2015/019524
申请日：2015-03-09
申请人： INTEL CORPORATION
发明人： MARIN, Brandon, C. , GHOSH DASTIDAR, Trina , SENEVIRATNE, Dilan , LI, Yonggang , CHAVA, Sirisha
IPC分类号： H01L21/3205
CPC分类号： H01L23/14 , H01L21/4846 , H01L23/145 , H01L23/49822 , H01L23/49866 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2924/15311 , H05K3/062 , H05K3/105 , H05K3/107 , H05K3/182 , H05K3/185 , H05K2201/0209 , H05K2203/107
摘要： Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed
摘要翻译：本公开的实施例描述了集成电路（IC）衬底的选择性金属化。在一个实施例中，集成电路（IC）衬底可以包括介电材料和具有分散在电介质材料中的多面体形状的金属晶体，并且与暴露于激光时要被烧蚀的配体结合，使得具有烧蚀的金属晶体配体被激活以提供用于金属的选择性无电沉积的催化剂。可以描述和/或要求保护其他实施例

4. 发明申请

WO2012078335A2 HYBRID-CORE THROUGH HOLES AND VIAS 审中-公开
标题翻译：通过孔和VIAS的混合核心
公开(公告)号：WO2012078335A2
公开(公告)日：2012-06-14
申请号：PCT/US2011/061239
申请日：2011-11-17
申请人： INTEL CORPORATION , ROY, Mihir K. , SALAMA, Islam A. , LI, Yonggang
发明人： ROY, Mihir K. , SALAMA, Islam A. , LI, Yonggang
IPC分类号： H05K3/46 , H05K3/40 , H01L23/12 , H01L23/045 , H01L23/055
CPC分类号： H05K3/422 , G06F1/183 , H01L23/492 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , Y10T29/49165 , H01L2924/00
摘要： A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.
摘要翻译：半导体器件衬底包括布置在第一芯的前表面和后表面上的层压芯的前部和后部。第一个铁芯有一个镀有金属的圆柱形电镀通孔，并填充有空芯材料。前部和后部有激光钻孔的锥形过孔，充满导电材料并与镀通孔相连。后部包括一个与前部连通的整体感应线圈。第一个核心和叠层核心形成一个带有整体电感线圈的混合核心半导体器件衬底。

5. 发明申请

WO2009042741A3 METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE 审中-公开
公开(公告)号：WO2009042741A3
公开(公告)日：2009-04-02
申请号：PCT/US2008/077612
申请日：2008-09-25
申请人： INTEL CORPORATION , BCHIR, Omar J. , JOMAA, Houssam , SALAMA, Islam A. , LI, Yonggang
发明人： BCHIR, Omar J. , JOMAA, Houssam , SALAMA, Islam A. , LI, Yonggang
IPC分类号： H01L21/306 , H01L21/304
摘要： A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.

6. 发明申请

WO2009006065A1 A METHOD OF FORMING A MULTILAYER SUBSTRATE CORE STRUCTURE USING SEQUENTIAL MICROVIA LASER DRILLING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD 审中-公开
标题翻译：使用顺序的微晶激光钻孔形成多层底物核心结构的方法和根据该方法形成的基底核心结构
公开(公告)号：WO2009006065A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/067847
申请日：2008-06-23
申请人： INTEL CORPORATION , LI, Yonggang , SALAMA, Islam , GURUMURTHY, Charan
发明人： LI, Yonggang , SALAMA, Islam , GURUMURTHY, Charan
IPC分类号： H05K3/46 , H05K3/00
CPC分类号： H05K3/422 , H05K3/0035 , H05K3/4602 , H05K3/4652 , H05K2201/0394 , H05K2201/09563 , Y10T29/49128 , Y10T29/49165
摘要： A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.
摘要翻译：一种制造衬底芯结构的方法，以及根据该方法形成的衬底芯结构。该方法包括：通过起始绝缘层激光钻探第一组通路孔; 用导电材料填充第一组通孔开口以提供第一组导电通孔; 在起始绝缘层的相对侧上提供第一和第二图案化导电层; 在所述第一图案化导电层上提供补充绝缘层; 激光钻穿通过补充绝缘层的第二组通孔; 用导电材料填充第二组通孔开口以提供第二组导电通路; 以及在所述补充绝缘层的暴露侧上提供补充图案化导电层，所述第二组导电通孔在其相对侧与所述第一图案化导电层和所述补充图案化导电层接触。

7. 发明申请

WO2018063398A1 METAL BASED CERAMIC FILLERS AS CATALYSTS FOR SELECTIVE ELECTROLESS METAL PLATING 审中-公开
标题翻译：金属基陶瓷填料作为选择性化学镀金属的催化剂
公开(公告)号：WO2018063398A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/055019
申请日：2016-09-30
申请人： INTEL CORPORATION , RAGHUNATHAN, Vivek , LI, Yonggang
发明人： RAGHUNATHAN, Vivek , LI, Yonggang
IPC分类号： H01L21/768
摘要： Embodiments include methods for selective electroless plating of dielectric layers and devices formed by such processes. According to an embodiment, patterned surfaces are formed in a dielectric layer that includes metallic ceramic fillers. In some embodiments, the patterned surfaces form a line opening and a via opening that exposes a conductive pad. In an embodiment, the metallic ceramic fillers are activated to form activated surfaces over the patterned surfaces. A first metal is then deposited into the via opening with a first electroless solution that is a bottom-up deposition process. Thereafter, embodiments include forming a seed layer over exposed portions of the activated surfaces. In an embodiment, mid-gap states of the activated surfaces have an energy level approximately equal to a reduction potential of metal ions in a second electroless solution. Embodiments may then include depositing a second metal into the via opening with a third electroless solution.
摘要翻译：实施方式包括用于选择性无电镀电介质层和通过这些工艺形成的器件的方法。根据一个实施例，图案化表面形成在包括金属陶瓷填料的介电层中。在一些实施例中，图案化表面形成暴露导电垫的线开口和通孔开口。在一个实施例中，金属陶瓷填料被激活以在图案化表面上形成活化表面。然后用第一种无电解决方案将第一种金属沉积到通孔开口中，该第一种无电解决方案是自底向上沉积工艺。此后，实施例包括在激活表面的暴露部分上形成种子层。在一个实施例中，激活表面的中间隙状态具有与第二无电解决方案中的金属离子的还原电位近似相等的能级。然后，实施例可以包括利用第三无电解决方案将第二金属沉积到通孔开口中。

8. 发明申请

WO2016133489A1 MICROELECTRONIC BUILD-UP LAYERS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：微电子建筑层及其形成方法
公开(公告)号：WO2016133489A1
公开(公告)日：2016-08-25
申请号：PCT/US2015/016072
申请日：2015-02-16
申请人： INTEL CORPORATION
发明人： MARIN, Brandon C. , GHOSH DASTIDAR, Trina , LI, Yonggang , SENEVIRATNE, Dilan
IPC分类号： H01L21/768
CPC分类号： H05K3/187 , H01L21/288 , H01L21/4857 , H01L21/76802 , H01L21/76829 , H01L21/76874 , H01L21/76877 , H01L23/49894 , H01L23/528 , H01L23/53228 , H01L23/5329 , H05K1/036 , H05K1/09 , H05K3/0032 , H05K3/105 , H05K3/182 , H05K2201/09036
摘要： A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.
摘要翻译：可以通过形成包含分散在其中的金属化催化剂的电介质材料的微电子介电层来形成堆积层，在微电子介电层上形成底漆层，以及通过底漆层形成凹陷并进入电介质材料层。活化层可以形成在凹陷内的暴露的微电子介电层中或其上，其中底漆层用作掩模。可以在活化层上形成金属层，例如用无电解方法。因此，可以通过用于形成凹部的工艺来精确地控制金属层沉积的分辨率。

9. 发明申请

WO2020005440A1 SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS 审中-公开
公开(公告)号：WO2020005440A1
公开(公告)日：2020-01-02
申请号：PCT/US2019/034250
申请日：2019-05-29
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , DARMAWIKARTA, Kristof , DUAN, Gang , LI, Yonggang , PAITAL, Sameer
IPC分类号： H01F17/00 , H01F5/00 , H01F27/28
摘要： Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

10. 发明申请

WO2017052813A1 IMPROVED PACKAGE INTEGRATED POWER INDUCTORS USING LITHOGRAPHICALLY DEFINED VIAS 审中-公开
标题翻译：使用光刻定义的VIAS改进的封装集成功率电感器
公开(公告)号：WO2017052813A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/046046
申请日：2016-08-08
申请人： INTEL CORPORATION
发明人： MANUSHAROW, Mathew J. , LI, Yonggang , LAMBERT, William J. , BHARATH, Krishna , ELSHERBINI, Adel A. , EID, Feras , ALEKSOV, Aleksandar , BRAUNISCH, Henning
IPC分类号： H01L49/02 , H01F17/00 , H01F41/04 , H01L21/768 , H01L21/027
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/24 , H01F41/041 , H01F41/042 , H01F2017/0073 , H01F2017/0086 , H01F2027/2809 , H01L21/486 , H01L23/49838 , H01L28/10 , H01L2224/16227
摘要： Embodiments of the invention include inductors integrated into a package substrate that have increased thicknesses due to the use of shaped vias, and methods of forming such packages. In an embodiment of the invention an inductor may be formed in a package substrate may include a first inductor line formed on the package substrate. In some embodiments, a shaped via may be formed over the first inductor line. Additional embodiments may include a dielectric layer that is formed over the package substrate, the first inductor line and around the shaped via. In one embodiment, a second inductor line may also be formed over the shaped via. Some embodiments of the invention may include an inductor that is a spiral inductor.
摘要翻译：本发明的实施例包括集成到封装基板中的电感器，其由于使用成形的通孔而具有增加的厚度，以及形成这种封装的方法。在本发明的一个实施例中，电感器可以形成在封装衬底中，可以包括形成在封装衬底上的第一电感线。在一些实施例中，可以在第一电感线上形成成形的通孔。另外的实施例可以包括形成在封装衬底，第一电感线和围绕成形通孔的介电层。在一个实施例中，也可以在成形通孔上形成第二电感线。本发明的一些实施例可以包括作为螺旋电感器的电感器。

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