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1. 发明申请

WO2012078335A2 HYBRID-CORE THROUGH HOLES AND VIAS 审中-公开
标题翻译：通过孔和VIAS的混合核心
公开(公告)号：WO2012078335A2
公开(公告)日：2012-06-14
申请号：PCT/US2011/061239
申请日：2011-11-17
申请人： INTEL CORPORATION , ROY, Mihir K. , SALAMA, Islam A. , LI, Yonggang
发明人： ROY, Mihir K. , SALAMA, Islam A. , LI, Yonggang
IPC分类号： H05K3/46 , H05K3/40 , H01L23/12 , H01L23/045 , H01L23/055
CPC分类号： H05K3/422 , G06F1/183 , H01L23/492 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , Y10T29/49165 , H01L2924/00
摘要： A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.
摘要翻译：半导体器件衬底包括布置在第一芯的前表面和后表面上的层压芯的前部和后部。第一个铁芯有一个镀有金属的圆柱形电镀通孔，并填充有空芯材料。前部和后部有激光钻孔的锥形过孔，充满导电材料并与镀通孔相连。后部包括一个与前部连通的整体感应线圈。第一个核心和叠层核心形成一个带有整体电感线圈的混合核心半导体器件衬底。

2. 发明申请

WO2011087573A2 THROUGH MOLD VIA POLYMER BLOCK PACKAGE 审中-公开
标题翻译：通过聚合物块包装通过模具
公开(公告)号：WO2011087573A2
公开(公告)日：2011-07-21
申请号：PCT/US2010/057436
申请日：2010-11-19
申请人： INTEL CORPORATION , ROY, Mihir K. , SALAMA, Islam A. , GURUMURTHY, Charavana K. , SANKMAN, Robert L.
发明人： ROY, Mihir K. , SALAMA, Islam A. , GURUMURTHY, Charavana K. , SANKMAN, Robert L.
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/49816 , H01L24/13 , H01L2224/16225 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.
摘要翻译：描述了用于在聚合物块中形成具有贯通模通孔的集成电路芯片封装的方法，并且描述了这种封装。例如，第一互连层可以形成在模制聚合物块上，其中第一互连层包括穿过第一聚合物层并连接到块的第一互连。然后，可以在第一互连层上形成至少一个第二互连层，其中第二互连层包括穿过第二聚合物层并且连接到第一互连层的第一互连的第二互连。然后可以通过模块形成模制过孔，进入第一互连层以及第一互连。贯穿模具通孔可以填充有焊料以形成接触第一互连并在块体上方延伸的凸块。其他实施例也被描述和要求保护。

3. 发明申请

WO2012087556A2 DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS 审中-公开
标题翻译：器件包装与具有嵌入线和金属定义的衬垫的基板
公开(公告)号：WO2012087556A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063409
申请日：2011-12-06
申请人： INTEL CORPORATION , HLAD, Mark S. , SALAMA, Islam A. , ROY, Mihir K. , WU, Tao , LIU, Yueli , LEE, Kyu Oh
发明人： HLAD, Mark S. , SALAMA, Islam A. , ROY, Mihir K. , WU, Tao , LIU, Yueli , LEE, Kyu Oh
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/563 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49866 , H01L23/50 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/1112 , H01L2224/11462 , H01L2224/11464 , H01L2224/11466 , H01L2224/119 , H01L2224/13005 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1601 , H01L2224/16225 , H01L2224/16238 , H01L2224/165 , H01L2224/2919 , H01L2224/73204 , H01L2224/81121 , H01L2224/81191 , H01L2224/81444 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2224/831 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01103 , H01L2924/01108 , H01L2924/12042 , H01L2924/14 , H01L2924/15321 , H01L2924/2064 , H01L2924/37001 , H01L2924/3841 , H05K1/113 , H05K3/107 , H05K3/3436 , H05K3/421 , H01L2924/00014 , H01L2924/00
摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
摘要翻译：封装基板实现减小的凸点间距及其封装组件。表面层金属特征被嵌入在表面层级介质层中，表面层从表面层级介质的顶表面突出，用于在没有阻焊层的情况下组装到具有焊接连接点的IC芯片上。封装基板的制作能够实现多层次的走线布线，每条走线布线层次都能够减小最小走线宽度和间距。

4. 发明申请

WO2009042741A3 METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE 审中-公开
公开(公告)号：WO2009042741A3
公开(公告)日：2009-04-02
申请号：PCT/US2008/077612
申请日：2008-09-25
申请人： INTEL CORPORATION , BCHIR, Omar J. , JOMAA, Houssam , SALAMA, Islam A. , LI, Yonggang
发明人： BCHIR, Omar J. , JOMAA, Houssam , SALAMA, Islam A. , LI, Yonggang
IPC分类号： H01L21/306 , H01L21/304
摘要： A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.

5. 发明申请

WO2009085509A1 SELECTIVE ELECTROLESS PLATING FOR ELECTRONIC SUBSTRATES 审中-公开
标题翻译：电子基板的选择性电镀镀层
公开(公告)号：WO2009085509A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/084731
申请日：2008-11-25
申请人： INTEL CORPORATION , JOMAA, Houssam , BCHIR, Omar J. , SALAMA, Islam A.
发明人： JOMAA, Houssam , BCHIR, Omar J. , SALAMA, Islam A.
IPC分类号： H01L23/48 , H01L23/52 , H01L21/60 , G05F1/00
CPC分类号： H05K3/107 , H05K3/0032 , H05K3/184 , H05K2203/0565 , H05K2203/1383 , Y10S438/94
摘要： In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.
摘要翻译：在一些实施例中，提出了用于电子基板的选择性无电镀。在这方面，引入了一种方法，包括在基板的表面上形成膜，设计用于防止化学镀催化剂的接种的膜，通过膜激光烧蚀基板的表面以形成沟槽，并且将表面的无电镀催化剂。还公开并要求保护其他实施例。

6. 发明申请

WO2018182597A1 MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER 审中-公开
公开(公告)号：WO2018182597A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024795
申请日：2017-03-29
申请人： INTEL CORPORATION , MAY, Robert Alan , SALAMA, Islam A. , BOYAPATI, Sri Ranga Sai , LI, Sheng , DARMAWIKARTA, Kristof , SANKMAN, Robert L. , ALUR, Amruthavalli Pallavi
发明人： MAY, Robert Alan , SALAMA, Islam A. , BOYAPATI, Sri Ranga Sai , LI, Sheng , DARMAWIKARTA, Kristof , SANKMAN, Robert L. , ALUR, Amruthavalli Pallavi
IPC分类号： H01L25/065 , H01L23/00 , H01L25/07
摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

7. 发明申请

WO2017039583A1 USE OF SACRIFICIAL MATERIAL TO COMPENSATE FOR THICKNESS VARIATION IN MICROELECTRONIC SUBSTRATES 审中-公开
标题翻译：使用材料补偿微电子基板厚度变化
公开(公告)号：WO2017039583A1
公开(公告)日：2017-03-09
申请号：PCT/US2015/047440
申请日：2015-08-28
申请人： INTEL CORPORATION , CHEN, Chi-Mon , LI, Yi , WU, Tao , ZHOU, Zheng , SALAMA, Islam A. , LIU, Yueli , ALUR, Amruthavalli P. , SHARMA, Nikhil
发明人： CHEN, Chi-Mon , LI, Yi , WU, Tao , ZHOU, Zheng , SALAMA, Islam A. , LIU, Yueli , ALUR, Amruthavalli P. , SHARMA, Nikhil
IPC分类号： H01L25/07 , H01L23/48
CPC分类号： H01L21/481 , H01L21/6835 , H01L23/13 , H01L23/145 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/131 , H01L2224/16227 , H01L2224/73204 , H01L2224/75744 , H01L2224/81002 , H01L2224/81005 , H01L2224/81192 , H01L2224/83104 , H01L2924/15159 , H01L2924/19105 , H01L2924/014 , H01L2924/00014
摘要： A microelectronic package may be fabricated by forming a microelectronic substrate having a front surface and a back surface, transferring thickness variation in the microelectronic substrate to the microelectronic substrate back surface by attaching the microelectronic substrate front surface to a first fixture, forming a sacrificial material over the microelectronic substrate back surface having a first surface opposing the microelectronic substrate back surface, removing the microelectronic substrate from the first substrate, attaching the sacrificial material first surface to a second fixture, and attaching at least one microelectronic device to the microelectronic substrate front surface. In another embodiment, a releasing layer may be disposed between the microelectronic substrate back surface and the sacrificial material.
摘要翻译：可以通过形成具有前表面和后表面的微电子衬底来制造微电子封装，通过将微电子衬底前表面附接到第一固定件，将微电子衬底中的厚度变化传递到微电子衬底背面，从而形成牺牲材料所述微电子衬底背表面具有与所述微电子衬底背表面相对的第一表面，从所述第一衬底移除所述微电子衬底，将所述牺牲材料第一表面附接到第二固定件，以及将至少一个微电子器件附接到所述微电子衬底前表面。在另一个实施例中，释放层可以设置在微电子衬底背表面和牺牲材料之间。

8. 发明申请

WO2018063316A1 DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGE 审中-公开
标题翻译：使用嵌入式多模互连桥的非常高密度路由的设备和方法
公开(公告)号：WO2018063316A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054739
申请日：2016-09-30
申请人： MAY, Robert Alan , JEN, Wei-Lun Kane , ROSCH, Jonathan , SALAMA, Islam A. , DARMAWIKARTA, Kristof
发明人： MAY, Robert Alan , JEN, Wei-Lun Kane , ROSCH, Jonathan , SALAMA, Islam A. , DARMAWIKARTA, Kristof
IPC分类号： H01L23/00 , H01L23/12 , H01L23/538
摘要： A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.
摘要翻译：公开了一种用于提供增强桥结构的设备和方法。沉积一组导电层和绝缘层并进行光刻处理。导电层具有uFLS路由。在底层结构上放置uFLS触点和裸片的桥接器，使裸片与uFLS触点和uFLS布线连接。对于基于核心的结构，在桥被放置在下面的结构上并且管芯通过中间导电层连接到桥上之后形成层。对于无芯结构，这些层形成在桥和载体上，在将管芯键合到桥上之前将其去除，并将管芯直接键合到桥上。

9. 发明申请

WO2016209244A1 INTEGRATED CIRCUIT STRUCTURES WITH RECESSED CONDUCTIVE CONTACTS FOR PACKAGE ON PACKAGE 审中-公开
标题翻译：集成电路结构与封装的封装导电性接触
公开(公告)号：WO2016209244A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037814
申请日：2015-06-25
申请人： INTEL CORPORATION
发明人： LEE, Kyu-Oh , SALAMA, Islam A. , VISWANATH, Ram S. , SANKMAN, Robert L. , SABI, Babak , CHAVALI, Sri Chaitra Jyotsna
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/48 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/05 , H01L24/11 , H01L24/17 , H01L25/105 , H01L2224/0401 , H01L2224/05147 , H01L2224/16225 , H01L2224/97 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311
摘要： Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed
摘要翻译：这里公开了具有用于封装在封装（PoP）上的凹陷导电触点的集成电路（IC）结构。例如，IC结构可以包括：具有第一抗蚀剂表面的IC封装; 设置在所述第一抗蚀剂表面中的凹部，其中所述凹部的底部包括第二抗蚀剂表面; 位于第一抗蚀剂表面处的第一多个导电触点; 以及位于第二抗蚀剂表面处的第二多个导电触点。可以公开和/或要求保护其他实施例

10. 发明申请

WO2018013311A1 PACKAGE WITH PASSIVATED INTERCONNECTS 审中-公开
标题翻译：包装与被钝化的相互连接
公开(公告)号：WO2018013311A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/038656
申请日：2017-06-22
申请人： INTEL CORPORATION
发明人： BOYAPATI, Sri Ranga Sai , MANEPALLI, Rahul N. , SENEVIRATNE, Dilan , PIETAMBARAM, Srinivas V. , DARMAWIKARTA, Kristof , MAY, Robert Alan , SALAMA, Islam A.
IPC分类号： H01L23/485 , H01L23/48 , H01L23/31 , H01L25/065
摘要： The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
摘要翻译：钝化层可以是可以覆盖半导体封装中的互连层的构建介电层和金属迹线的任何合适的介电材料。可以在增层介质中形成通孔，并且可以从通孔的底部去除钝化层。通过去除通孔底部的钝化层，还可以从通孔底部去除任何残留的积累电介质。因此去除残余积层电介质可能不需要否则会使金属和/或电介质表面变粗糙的去污处理。通过使用钝化层实现的更平滑的金属和/或电介质表面可以允许更大的工艺宽容度和/或灵活性来制造相对较小的尺寸互连特征和/或相对提高的信号频率和完整性。

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