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1. 发明申请

WO2022231712A1 AN ELECTRONIC SUBSTRATE HAVING AN EMBEDDED ETCH STOP TO CONTROL CAVITY DEPTH IN GLASS LAYERS THEREIN 审中-公开
公开(公告)号：WO2022231712A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/020302
申请日：2022-03-15
申请人： INTEL CORPORATION
发明人： ECTON, Jeremy , MARIN, Brandon , PIETAMBARAM, Srinivas , NAD, Suddhasattwa
IPC分类号： H01L23/15 , H01L23/498 , H01L23/492 , H01L23/48
摘要： An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

2. 发明申请

WO2023038786A1 NESTED GLASS PACKAGING ARCHITECTURE FOR HYBRID ELECTRICAL AND OPTICAL COMMUNICATION DEVICES 审中-公开
公开(公告)号：WO2023038786A1
公开(公告)日：2023-03-16
申请号：PCT/US2022/041126
申请日：2022-08-22
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , MARIN, Brandon C. , MALLIK, Debendra , IBRAHIM, Tarik A. , ECTON, Jeremy , KARHADE, Omkar G. , PENMECHA, Bharat Prasad , LI, Xiaoqian , DESHPANDE, Nitin A. , MODI, Mitul , NIE, Bai
IPC分类号： H01L25/16 , G02B6/12 , H01L23/13 , H01L23/15 , H01L23/538 , H01L21/52
摘要： An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

3. 发明申请

WO2022108647A1 HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES 审中-公开
公开(公告)号：WO2022108647A1
公开(公告)日：2022-05-27
申请号：PCT/US2021/049666
申请日：2021-09-09
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , MARIN, Brandon C. , PAITAL, Sameer , VADLIMANI, Sai , MANEPALLI, Rahul N. , LI, Xiaoqian , POTHUKUCHI, Suresh V. , SHARAN, Sujit , SARKAR, Arnab , KARHADE, Omkar , DESHPANDE, Nitin , PRATAP, Divya , ECTON, Jeremy , MALLIK, Debendra , MAHAJAN, Ravindranath V. , ZHANG, Zhichao , AYGÜN, Kemal , NIE, Bai , DARMAWIKARTA, Kristof , JAUSSI, James E. , GAMBA, Jason M. , CASPER, Bryan K. , DUAN, Gang , INTI, Rajesh , MANSURI, Mozhgan , JADHAV, Susheel , BROWN, Kenneth , AGRAWAL, Ankar , DOBRIYAL, Priyanka
IPC分类号： G02B6/42 , H01L31/0203 , H01L23/538 , H01L25/16
摘要： Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

4. 发明申请

WO2019066813A1 METHOD, DEVICE AND SYSTEM FOR PROVIDING ETCHED METALLIZATION STRUCTURES 审中-公开
公开(公告)号：WO2019066813A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053786
申请日：2017-09-27
申请人： INTEL CORPORATION
发明人： ECTON, Jeremy , HAEHN, Nicholas , OJEDA, Oscar , ROY, Arnab , WHITE, Timothy , NAD, Suddhasattwa , WANG, Hsin-Wei
IPC分类号： H01L21/768 , H01L21/306
摘要： Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

5. 发明公开

EP4203004A3 STRESS ARREST LIP ON COPPER PAD FOR LOW ROUGHNESS COPPER 审中-实审
公开(公告)号：EP4203004A3
公开(公告)日：2023-08-09
申请号：EP22207569.9
申请日：2022-11-15
申请人： Intel Corporation
发明人： KONG, Jieying , ANGOUA, Bainye , SENEVIRATNE, Dilan , BRYKS, Whitney , ECTON, Jeremy
IPC分类号： H01L23/00
摘要： A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.

6. 发明公开

EP4394860A1 ARCHITECTURES AND METHODS FOR METAL LAMINATION ON A GLASS LAYER 审中-公开
公开(公告)号：EP4394860A1
公开(公告)日：2024-07-03
申请号：EP23201007.4
申请日：2023-09-29
申请人： INTEL Corporation
发明人： MARIN, Brandon , KANDANUR, Sashi , PIETAMBARAM, Srinivas , DUAN, Gang , ECTON, Jeremy
IPC分类号： H01L23/15 , H01L23/498
CPC分类号： H01L23/49827 , H01L23/15 , H01L21/486
摘要： Architectures and methods for metal lamination on a glass layer or glass core. The architectures implement dummy anchors to prevent or reduce the delamination of conductive materials from glass surfaces. The anchors hold the conductive pads and conductive material planes down to the glass surface. The architecture includes various combinations of end anchors and through glass via (TGV) anchors.

7. 发明公开

EP4184569A3 MICROELECTRONIC PACKAGES WITH REGULAR SOLDER JOINTS AND NO-REMELT, FULL INTERMETALLIC COMPOUND JOINTS BETWEEN TWO SUBSTRATES 审中-实审
公开(公告)号：EP4184569A3
公开(公告)日：2023-08-09
申请号：EP22201685.9
申请日：2022-10-14
申请人： INTEL Corporation
发明人： SHAN, Bohan , CHEN, Haobo , KARHADE, Omkar , SANKARASUBRAMANIAN, Malavarayan , XU, Dingying , DUAN, Gang , NIE, Bai , GUO, Xiaoying , DARMAWIKARTA, Kristof , FENG, Hongxia , PIETAMBARAM, Srinivas V. , ECTON, Jeremy
IPC分类号： H01L23/485 , H01L21/603 , H01L25/065 , H05K3/34
摘要： In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

8. 发明公开

EP4386827A1 LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE 审中-公开
公开(公告)号：EP4386827A1
公开(公告)日：2024-06-19
申请号：EP23199562.2
申请日：2023-09-25
申请人： INTEL Corporation
发明人： DUAN, Gang , MANEPALLI, Rahul , PIETAMBARAM, Srinivas , MARIN, Brandon , NAD, Suddhasattwa , ECTON, Jeremy
IPC分类号： H01L23/00 , H01L25/065 , H01L25/00
CPC分类号： H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L24/16 , H01L24/17
摘要： An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

9. 发明公开

EP4184569A2 MICROELECTRONIC PACKAGES WITH REGULAR SOLDER JOINTS AND NO-REMELT, FULL INTERMETALLIC COMPOUND JOINTS BETWEEN TWO SUBSTRATES 审中-实审
公开(公告)号：EP4184569A2
公开(公告)日：2023-05-24
申请号：EP22201685.9
申请日：2022-10-14
申请人： INTEL Corporation
发明人： SHAN, Bohan , CHEN, Haobo , KARHADE, Omkar , SANKARASUBRAMANIAN, Malavarayan , XU, Dingying , DUAN, Gang , NIE, Bai , GUO, Xiaoying , DARMAWIKARTA, Kristof , FENG, Hongxia , PIETAMBARAM, Srinivas V. , ECTON, Jeremy
IPC分类号： H01L23/485 , H01L21/603 , H01L25/065 , H05K3/34
摘要： In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

10. 发明公开

EP3716328A3 HYBRID FINE LINE SPACING ARCHITECTURE FOR BUMP PITCH SCALING 审中-公开
公开(公告)号：EP3716328A3
公开(公告)日：2020-11-25
申请号：EP20156771.6
申请日：2020-02-11
申请人： INTEL Corporation
发明人： NAD, Suddhasattwa , ECTON, Jeremy , NIE, Bai , MANEPALLI, Rahul N. , WALL, Marcel Arlan
IPC分类号： H01L25/065
摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

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