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1. 发明申请

WO2019066981A1 PARALLEL PROCESSING BASED ON INJECTION NODE BANDWIDTH 审中-公开
公开(公告)号：WO2019066981A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054663
申请日：2017-09-30
申请人： INTEL CORPORATION
发明人： VAIDYANATHAN, Karthikeyan , SRIDHARAN, Srinivas , DAS, Dipankar
IPC分类号： G06F9/38
摘要： A technique includes performing a collective operation among multiple nodes of a parallel processing computer system using multiple parallel processing stages. The technique includes regulating an ordering of the parallel processing stages so that an initial stage of the plurality of parallel processing stages is associated with a higher node injection bandwidth than a subsequent stage of the plurality of parallel processing stages.

2. 发明申请

WO2018034682A1 APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS 审中-公开
标题翻译：用于神经网络的装置，方法和系统
公开(公告)号：WO2018034682A1
公开(公告)日：2018-02-22
申请号：PCT/US2016/053980
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： VENKATARAMANI, Swagath , DAS, Dipankar , RANJAN, Ashish , BANERJEE, Subarno , AVANCHA, Sasikanth , JAGANNATHAN, Ashok , DURG, Ajaya V. , NAGARAJ, Dheemanth , KAUL, Bharat , RAGHUNATHAN, Anand
IPC分类号： G06N3/02 , G06N3/06
摘要： Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
摘要翻译：描述了与处理神经网络有关的方法和设备。在一个实施例中，处理神经网络的设备包括通过互连耦合的多个完全连接的层芯片; 多个卷积层芯片，每个卷积层芯片通过互连耦合到所述多个完全连接的层芯片中的各个完全连接的层芯片，并且所述多个完全连接的层芯片中的每一个和所述多个卷积层芯片包括互连，前向传播计算密集瓦片，后向传播计算密集瓦片以及第一内存密集瓦片和第二内存密集瓦片之间的一列计算密集瓦片的权重梯度计算密集瓦片。

3. 发明申请

WO2022271226A1 SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY 审中-公开
公开(公告)号：WO2022271226A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/020408
申请日：2022-03-15
申请人： INTEL CORPORATION
发明人： PARRA, Jorge , FU, Fangwen , MAIYURAN, Subramaniam , GEORGE, Varghese , MACPHERSON, Mike , PAL, Supratim , GURRAM, Chandra , GANAPATHY, Sabareesh , AVANCHA, Sasikanth , VOOTURI, Dharma Teja , MELLEMPUDI, Naveen , DAS, Dipankar
IPC分类号： G06F17/16 , G06F9/00 , G06F15/8046 , G06F7/523 , G06F7/5443 , G06F9/3001 , G06F9/30036
摘要： A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.

4. 发明申请

WO2018034681A1 APPARATUSES, METHODS, AND SYSTEMS FOR ACCESS SYNCHRONIZATION IN A SHARED MEMORY 审中-公开
标题翻译：用于在共享存储器中访问同步的装置，方法和系统
公开(公告)号：WO2018034681A1
公开(公告)日：2018-02-22
申请号：PCT/US2016/053967
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： VENKATARAMANI, Swagath , DAS, Dipankar , AVANCHA, Sasikanth , RANJAN, Ashish , BANERJEE, Subarno , KAUL, Bharat , RAGHUNATHAN, Anand
IPC分类号： G06F9/32 , G06F9/30
摘要： Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.
摘要翻译：描述与共享存储器中的访问同步有关的系统，方法和装置。在一个实施例中，处理器包括：解码器，将指令解码为解码指令;以及执行单元，执行解码指令以：接收要跟踪的存储器地址的第一输入操作数和允许序列的第二输入操作数的内存访问内存地址，并导致内存访问块违反内存访问内存地址的允许顺序。在一个实施例中，与执行单元分开的电路将用于存储器访问请求的存储器地址与跟踪表中的一个或多个存储器地址进行比较，并且当访问类型违反对应的允许的存储器访问请求时阻止用于存储器访问请求的存储器访问内存访问存储器访问请求的内存地址序列。

5. 发明公开

EP3783479A1 OPTIMIZED COMPUTE HARDWARE FOR MACHINE LEARNING OPERATIONS 审中-公开
公开(公告)号：EP3783479A1
公开(公告)日：2021-02-24
申请号：EP20200955.1
申请日：2018-04-30
申请人： INTEL Corporation
发明人： DAS, Dipankar , GRAMUNT, Roger , SMELYANSKIY, Mikhail , CORBAL, Jesus , MUDIGERE, Dheevatsa , MELLEMPUDI, Naveen K. , HEINECKE, Alexander F.
IPC分类号： G06F9/30
摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a fetch unit to fetch a single instruction having multiple input operands, wherein the multiple input operands have an unequal bit-length, a first input operand having a first bit-length and a second input operand having a second bit-length; a decode unit to decode the single instruction into a decoded instruction; an operand length unit to determine a smaller bit-length of the first bit-length and the second bit-length; and a compute unit to perform a matrix operation on the multiple input operands to generate an output value having a bit length of the smaller bit length.

6. 发明公开

EP3688577A1 PARALLEL PROCESSING BASED ON INJECTION NODE BANDWIDTH 审中-公开
公开(公告)号：EP3688577A1
公开(公告)日：2020-08-05
申请号：EP17927199.4
申请日：2017-09-30
申请人： Intel Corporation
发明人： VAIDYANATHAN, Karthikeyan , SRIDHARAN, Srinivas , DAS, Dipankar
IPC分类号： G06F9/38

7. 发明公开

EP3506095A2 COMMUNICATION OPTIMIZATIONS FOR DISTRIBUTED MACHINE LEARNING 审中-公开
公开(公告)号：EP3506095A2
公开(公告)日：2019-07-03
申请号：EP18209320.3
申请日：2018-11-29
申请人： INTEL Corporation
发明人： SRIDHARAN, Srinivas , VAIDYANATHAN, Karthikeyan , DAS, Dipankar , SAKTHIVEL, Chandrasekaran , SMORKALOV, Mikhail E.
IPC分类号： G06F9/50
摘要： Embodiments described herein provide a system to configure distributed training of a neural network, the system comprising memory to store a library to facilitate data transmission during distributed training of the neural network; a network interface to enable transmission and receipt of configuration data associated with a set of worker nodes, the worker nodes configured to perform distributed training of the neural network; and a processor to execute instructions provided by the library, the instructions to cause the processor to create one or more groups of the worker nodes, the one or more groups of worker nodes to be created based on a communication pattern for messages to be transmitted between the worker nodes during distributed training of the neural network.

8. 发明公开

EP3407183A3 OPTIMIZED COMPUTE HARDWARE FOR MACHINE LEARNING OPERATIONS 有权
公开(公告)号：EP3407183A3
公开(公告)日：2019-02-13
申请号：EP18170154.1
申请日：2018-04-30
申请人： INTEL Corporation
发明人： DAS, Dipankar , GRAMUNT, Roger , SMELYANSKIY, Mikhail , CORBAL, Jesus , MUDIGERE, Dheevatsa , MELLEMPUDI, Naveen K. , HEINECKE, Alexander F.
IPC分类号： G06F9/30
摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a fetch unit to fetch a single instruction having multiple input operands, wherein the multiple input operands have an unequal bit-length, a first input operand having a first bit-length and a second input operand having a second bit-length; a decode unit to decode the single instruction into a decoded instruction; an operand length unit to determine a smaller bit-length of the first bit-length and the second bit-length; and a compute unit to perform a matrix operation on the multiple input operands to generate an output value having a bit length of the smaller bit length.

9. 发明公开

EP4325350A3 INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS 审中-实审
公开(公告)号：EP4325350A3
公开(公告)日：2024-05-15
申请号：EP23213442.9
申请日：2019-02-28
申请人： Intel Corporation
发明人： DAS, Dipankar , MELLEMPUDI, Naveen K. , DUTTA, Mrinmay , KUMAR, Arun , MUDIGERE, Dheevatsa , KUNDU, Abhisek
IPC分类号： G06F7/48 , G06F9/30
CPC分类号： G06F7/483 , G06F2207/38220130101 , G06F9/30036 , G06F9/30065 , G06N3/063 , G06F9/30014 , G06F7/5443 , G06F9/3887
摘要： Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor comprises: fetch circuitry to fetch a single multiply-accumulate (MAC) instruction having fields to indicate an opcode, a destination, a first source vector having a first element width, and a second source vector having a second element width that is smaller than the first element width; decode circuitry to decode the fetched single MAC instruction; and a single instruction multiple data (SIMD) execution circuit to execute the single MAC instruction and perform multiply-accumulate operations within each processing lane of a plurality of processing lanes, the multiply-accumulate operations in each processing lane including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products, and accumulating the subset of products with an accumulation data element corresponding to the processing lane to generate a result data element corresponding to the processing lane, the result data element each having a width greater than the first element width and the second element width.

10. 发明公开

EP4325350A2 INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS 审中-实审
公开(公告)号：EP4325350A2
公开(公告)日：2024-02-21
申请号：EP23213442.9
申请日：2019-02-28
申请人： Intel Corporation
发明人： DAS, Dipankar , MELLEMPUDI, Naveen K. , DUTTA, Mrinmay , KUMAR, Arun , MUDIGERE, Dheevatsa , KUNDU, Abhisek
IPC分类号： G06F7/48
摘要： Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor comprises: fetch circuitry to fetch a single multiply-accumulate (MAC) instruction having fields to indicate an opcode, a destination, a first source vector having a first element width, and a second source vector having a second element width that is smaller than the first element width; decode circuitry to decode the fetched single MAC instruction; and a single instruction multiple data (SIMD) execution circuit to execute the single MAC instruction and perform multiply-accumulate operations within each processing lane of a plurality of processing lanes, the multiply-accumulate operations in each processing lane including: multiplying a subset of elements of the first source vector by corresponding elements of the second source vector to produce a corresponding subset of products, and accumulating the subset of products with an accumulation data element corresponding to the processing lane to generate a result data element corresponding to the processing lane, the result data element each having a width greater than the first element width and the second element width.

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