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1. 发明申请

WO2008154230A2 METHOD AND APPARATUS FOR EXPANSION KEY GENERATION FOR BLOCK CIPHERS 审中-公开
标题翻译：用于块式切片机的扩展关键生成的方法和装置
公开(公告)号：WO2008154230A2
公开(公告)日：2008-12-18
申请号：PCT/US2008/065685
申请日：2008-06-03
申请人： INTEL CORPORATION , OZTURK, Erdinc , YAP, Kirk, S. , WOLRICH, Gilbert , FEGHALI, Wajdi , GOPAL, Vindoh
发明人： OZTURK, Erdinc , YAP, Kirk, S. , WOLRICH, Gilbert , FEGHALI, Wajdi , GOPAL, Vindoh
IPC分类号： H04L9/30
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12 , H04L2209/24
摘要： A key scheduler performs a key-expansion to generate round keys for AES encryption and decryption just-in-time for each AES round. The key scheduler pre- computes slow operations in a current clock cycle to reduce the critical delay path for computing the round key for a next AES round.
摘要翻译：密钥调度程序执行密钥扩展，以便为每个AES轮次准时生成AES加密和解密的循环密钥。密钥调度器预先计算当前时钟周期中的慢速操作，以减少用于计算下一个AES循环的循环密钥的关键延迟路径。

2. 发明申请

WO2009085489A2 METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) 审中-公开
标题翻译：有效可编程循环冗余校验（CRC）的方法和装置
公开(公告)号：WO2009085489A2
公开(公告)日：2009-07-09
申请号：PCT/US2008/084571
申请日：2008-11-24
申请人： INTEL CORPORATION , GOPAL, Vindoh , OZTURK, Erdinc , WOLRICH, Gilbert , FEGHALI, Wajdi
发明人： GOPAL, Vindoh , OZTURK, Erdinc , WOLRICH, Gilbert , FEGHALI, Wajdi
IPC分类号： G06F9/46 , G06F13/10 , G06F11/00
CPC分类号： G06F7/724 , G06F7/72 , H03M13/09
摘要： A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.
摘要翻译：一种用于优化循环冗余校验（CRC）电路中的多个缩减级中的每一个的方法和设备，以产生用于数据块的残差减少区，用于执行减小同时保持相同通过减少逻辑的多个阶段延迟。 Karatsuba算法，CRC减少电路不同阶段的经典乘法和串行分割的混合组合导致平均面积减少约20％，而关键路径延迟没有减少。

3. 发明申请

WO2007095397A3 PROGRAMMABLE PROCESSING UNIT 审中-公开
公开(公告)号：WO2007095397A3
公开(公告)日：2007-08-23
申请号：PCT/US2007/004402
申请日：2007-02-14
申请人： INTEL CORPORATION , CUTTER, Daniel , FEGHALI, Wajdi , HASENPLAUGH, William , WOLRICH, Gilbert , GOPAL, Vindoh
发明人： CUTTER, Daniel , FEGHALI, Wajdi , HASENPLAUGH, William , WOLRICH, Gilbert , GOPAL, Vindoh
IPC分类号： G06F15/76
摘要： In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

4. 发明申请

WO2008079624A1 HIGH PERFORMANCE RAID-6 SYSTEM ARCHITECTURE WITH PATTERN MATCHING 审中-公开
标题翻译：高性能RAID-6系统架构与图案匹配
公开(公告)号：WO2008079624A1
公开(公告)日：2008-07-03
申请号：PCT/US2007/086672
申请日：2007-12-06
申请人： INTEL CORPORATION , GOPAL, Vindoh , WOLRICH, Gilbert , YAP, Kirk , FEGHALI, Wajdi , VRANICH, John , OTTAVI, Robert
发明人： GOPAL, Vindoh , WOLRICH, Gilbert , YAP, Kirk , FEGHALI, Wajdi , VRANICH, John , OTTAVI, Robert
IPC分类号： G06F3/06
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
摘要翻译：加速单元从处理器卸载计算密集型任务。加速单元包括两个数据处理路径，每个数据处理路径均具有算术逻辑单元并且共享单个乘法器单元。每个数据处理路径可以在相同的数据上并行地执行可配置的操作。提供特殊的多路复用器路径和指令以允许通过加速单元在数据的单程中在条带上计算P和Q型综合征。

5. 发明申请

WO2008002828A2 MODULAR REDUCTION USING FOLDING 审中-公开
标题翻译：使用折叠模块化减少
公开(公告)号：WO2008002828A2
公开(公告)日：2008-01-03
申请号：PCT/US2007/071829
申请日：2007-06-21
申请人： INTEL CORPORATION , HASENPLAUGH, William , GOPAL, Vindoh , GAUBATZ, Gunnar
发明人： HASENPLAUGH, William , GOPAL, Vindoh , GAUBATZ, Gunnar
CPC分类号： G06F7/72
摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N' = N H 2 f mod M + N L and, subsequently, determining N' mod M.
摘要翻译：描述技术来确定N mod M，其中N是具有n位宽度的数字，M是具有m位宽度的数字。这些技术通常涉及确定N'= N H 2 H 2 mod M + N L L，并且随后确定N'mod M.

6. 发明申请

WO2008002822A2 MULPTIPLYING TWO NUMBERS 审中-公开
标题翻译：多选两个数字
公开(公告)号：WO2008002822A2
公开(公告)日：2008-01-03
申请号：PCT/US2007/071746
申请日：2007-06-21
申请人： INTEL CORPORATION , HASENPLAUGH, William , GOPAL, Vindoh , GAUBATZ, Gunnar , BACE, Matthew
发明人： HASENPLAUGH, William , GOPAL, Vindoh , GAUBATZ, Gunnar , BACE, Matthew
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译：描述了将两个数字A和B相乘的技术。通常，乘法是通过在A和B的段上使用Karatsuba乘法并基于最显着的值调整Karatsuba乘法 A和B的位。

7. 发明申请

WO2015021380A1 INSTRUCTION AND LOGIC TO PROVIDE A SECURE CIPHER HASH ROUND FUNCTIONALITY 审中-公开
标题翻译：指导和逻辑提供安全的水龙头功能
公开(公告)号：WO2015021380A1
公开(公告)日：2015-02-12
申请号：PCT/US2014/050339
申请日：2014-08-08
申请人： INTEL CORPORATION
发明人： GOPAL, Vindoh , FEGHALI, Wajdi K.
IPC分类号： H04L9/06 , G06F9/30
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , H04L9/0625
摘要： Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.
摘要翻译：指令和逻辑提供安全密码散列算法的圆功能。一些实施例包括处理器，包括：解码级，用于解码用于安全密码散列算法的指令，指定源数据的第一指令以及一个或多个键操作数。处理器执行单元响应于解码的指令，使用一个或多个键操作数对源数据执行一次或多次安全密码散列算法循环迭代，并将该指令的结果存储在目的地寄存器中。该指令的一个实施例使用诸如DES或TDES之类的Feistel密码算法来指定安全密码散列算法的圆迭代。在一个实施例中，该指令的结果可以用于从整个处理资源集合的负载平衡请求请求生成资源分配。

8. 发明公开

EP2115562A1 HIGH PERFORMANCE RAID-6 SYSTEM ARCHITECTURE WITH PATTERN MATCHING 有权
标题翻译：与模式比较高性能的RAID-6系统架构
公开(公告)号：EP2115562A1
公开(公告)日：2009-11-11
申请号：EP07865319.3
申请日：2007-12-06
申请人： Intel Corporation
发明人： GOPAL, Vindoh , WOLRICH, Gilbert , YAP, Kirk , FEGHALI, Wajdi , VRANICH, John , OTTAVI, Robert
IPC分类号： G06F3/06
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.

9. 发明授权

EP2115562B1 HIGH PERFORMANCE RAID-6 SYSTEM ARCHITECTURE WITH PATTERN MATCHING 有权
标题翻译：与模式比较高性能的RAID-6系统架构
公开(公告)号：EP2115562B1
公开(公告)日：2013-01-23
申请号：EP07865319.3
申请日：2007-12-06
申请人： Intel Corporation
发明人： GOPAL, Vindoh , WOLRICH, Gilbert , YAP, Kirk , FEGHALI, Wajdi , VRANICH, John , OTTAVI, Robert
IPC分类号： G06F11/10 , G06F7/72
CPC分类号： G06F11/1076 , G06F2211/1057

10. 发明公开

EP3031167A1 INSTRUCTION AND LOGIC TO PROVIDE A SECURE CIPHER HASH ROUND FUNCTIONALITY 有权
标题翻译： COMMAND和逻辑提供了一个安全的密码HASHRUNDENFUNKTIONALITÄT
公开(公告)号：EP3031167A1
公开(公告)日：2016-06-15
申请号：EP14834842.8
申请日：2014-08-08
申请人： Intel Corporation
发明人： GOPAL, Vindoh , FEGHALI, Wajdi K.
IPC分类号： H04L9/06 , G06F9/30
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , H04L9/0625
摘要： Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.

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