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1. 发明申请

WO2013100989A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA DECODING ON PACKED DATA ELEMENTS 审中-公开
标题翻译：用于对包装数据元素进行DELTA解码的系统，设备和方法
公开(公告)号：WO2013100989A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067640
申请日：2011-12-28
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , WILLHALM, Thomas , DRYSDALE, Tracy Garrett
发明人： OULD-AHMED-VALL, Elmoustapha , WILLHALM, Thomas , DRYSDALE, Tracy Garrett
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/3013 , H04N19/42
摘要： Embodiments of systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a destination using a single vector packed delta decode instruction are described.
摘要翻译：描述了用于对源的压缩数据元素执行增量解码并使用单个向量压缩增量解码指令将结果存储在目的地的打包数据元素中的系统，装置和方法的实施例。

2. 发明申请

WO2017112233A1 HARDWARE ACCELERATORS AND METHODS FOR STATEFUL COMPRESSION AND DECOMPRESSION OPERATIONS 审中-公开
标题翻译：硬件加速器和状态压缩和减压操作的方法
公开(公告)号：WO2017112233A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063208
申请日：2016-11-21
申请人： INTEL CORPORATION
发明人： DRYSDALE, Tracy Garrett , GUILFORD, James D. , GOPAL, Vinodh , WOLRICH, Gilbert M. , KUKUNAS, James T.
IPC分类号： G06F9/30
CPC分类号： G06F9/466 , G06F9/5061 , G06F9/544 , G06F9/546 , G06F2209/509
摘要： Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.
摘要翻译：描述了与有状态压缩和解压缩操作有关的方法和装置。在一个实施例中，硬件处理器包括用于执行线程并卸载压缩和解压缩线程中的至少一个的核以及用于执行压缩和解压缩线程中的至少一个以消耗输入并生成输出的硬件压缩和解压缩加速器数据，其中硬件压缩和解压缩加速器耦合到多个输入缓冲器以存储输入数据，多个输出缓冲器以存储输出数据，输入缓冲器描述符阵列具有用于每个相应输入缓冲器的条目，输入具有用于每个相应输入缓冲器的相应响应条目的缓冲器响应描述符阵列，具有用于每个相应输出缓冲器的条目的输出缓冲器描述符阵列以及具有用于每个相应输出缓冲器的相应响应条目的输出缓冲器响应描述符阵列。 >

3. 发明公开

EP4398113A2 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 审中-公开
公开(公告)号：EP4398113A2
公开(公告)日：2024-07-10
申请号：EP24178028.7
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F12/08
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3009 , G06F9/30189 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3877 , G06F9/4411 , G06F9/45504 , G06F9/4881 , G06F9/5027 , G06F9/30181 , G06F9/30076 , Y02D10/00 , G06F9/38585 , G06F9/3858
摘要： The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.

4. 发明公开

EP4083804A1 HARDWARE ACCELERATORS AND METHODS FOR OFFLOAD OPERATIONS 审中-公开
公开(公告)号：EP4083804A1
公开(公告)日：2022-11-02
申请号：EP22180233.3
申请日：2017-08-30
申请人： Intel Corporation
发明人： DRYSDALE, Tracy Garrett , GOPAL, Vinodh , GUILFORD, James D.
IPC分类号： G06F9/54 , G06F9/50 , G06F9/30 , G06F12/084
摘要： Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.

5. 发明公开

EP4089531A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 有权
公开(公告)号：EP4089531A1
公开(公告)日：2022-11-16
申请号：EP22180798.5
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/38 , G06F12/08
摘要： The present disclosure provides an apparatus comprising an accelerator; a local memory comprising a plurality of stacked dynamic random access memory, DRAM, dies; a silicon bridge to couple the accelerator to the plurality of stacked DRAM dies, wherein connections between the accelerator and the plurality of stacked DRAM dies run through the silicon bridge. The accelerator comprising a plurality of processing elements to perform processing tasks allocated by an external processor; a cache coherent interface to couple the accelerator to the external processor, the cache coherent interface to ensure that data stored in the local memory and/or an accelerator cache is coherent with data stored in a system memory and caches of the external processor; and logic to map a virtual memory space to heterogeneous forms of physical system memory including the local memory and the system memory, the accelerator and the external processor to both use the virtual memory space to access corresponding portions of the local memory and the system memory.

6. 发明公开

EP3812900A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 有权
公开(公告)号：EP3812900A1
公开(公告)日：2021-04-28
申请号：EP20207505.7
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/48 , G06F9/38
摘要： The present disclosure provides apparatus comprising a silicon interposer, a communication fabric, an accelerator die comprising a plurality of computing elements to simultaneously perform operations on a plurality of matrix data elements. The apparatus comprising a plurality of dot-product engines, the plurality of dot-product engines to compute a plurality of dot products on the matrix data elements to generate a plurality of result matrix data elements, a buffer or cache to store a plurality of matrix data elements a memory controller coupled to the communication fabric and a stacked DRAM that stacks a plurality of DRAM dies vertically on the silicon interposer substrate coupled to the accelerator die.

8. 发明公开

EP4120070A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 有权
公开(公告)号：EP4120070A1
公开(公告)日：2023-01-18
申请号：EP22193012.6
申请日：2016-12-31
申请人： INTEL Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/30
摘要： The present disclosure provides a method and an apparatus comprising a decoder to decode an enqueue command instruction, execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to: generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations and to store the work descriptor to a work queue.

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