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1. 发明申请

WO2013101122A1 SECURE ERROR HANDLING 审中-公开
标题翻译：安全错误处理
公开(公告)号：WO2013101122A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067966
申请日：2011-12-29
申请人： INTEL CORPORATION , NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J. , YIGZAW, Theodros , VARGAS, Andrew , KURAMKOTE, Rajendra
发明人： NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J. , YIGZAW, Theodros , VARGAS, Andrew , KURAMKOTE, Rajendra
IPC分类号： G06F21/22 , G06F9/22
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/3664 , G06F21/57
摘要： Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
摘要翻译：一些实施例包括操作系统和平台。该平台包括具有错误寄存器的处理器。操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。描述和要求保护其他实施例。

2. 发明申请

WO2015080717A1 METHOD AND APPARATUS FOR SERVER PLATFORM ARCHITECTURES THAT ENABLE SERVICEABLE NONVOLATILE MEMORY MODULES 审中-公开
标题翻译：使用可维修非易失性存储器模块的服务器平台架构的方法和设备
公开(公告)号：WO2015080717A1
公开(公告)日：2015-06-04
申请号：PCT/US2013/072159
申请日：2013-11-27
申请人： INTEL CORPORATION , ZIAKAS, Dimitrios , COURY, Bassam N. , KUMAR, Mohan J. , NACHIMUTHU, Murugasamy K. , DANG, Thi , WUNDERLICH, Russell J.
发明人： ZIAKAS, Dimitrios , COURY, Bassam N. , KUMAR, Mohan J. , NACHIMUTHU, Murugasamy K. , DANG, Thi , WUNDERLICH, Russell J.
IPC分类号： G06F15/76
CPC分类号： G06F15/7803 , G06F11/1662 , G06F2201/805
摘要： Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
摘要翻译：实现服务器架构的系统和方法可以方便计算机系统中的存储器组件的维护。这些系统和方法采用非易失性存储/存储模块，其中包括可用于系统内存和大容量存储的非易失性存储器（NVM）以及固件存储器。相应的NVM /存储模块可以被接收在计算机系统的前部或后部装载槽中。该系统和方法进一步采用单插槽，双插槽或四插槽处理器，其中每个处理器通过一个或多个存储器和/或输入可通信地耦合到布置在前装载或后装载槽中的至少一些NVM /存储模块 /输出（I / O）通道。通过采用可以在计算机系统的前端或后端加载的接收的NVM /存储模块，系统和方法提供了迄今为止在实现常规服务器架构的计算机系统中无法实现的存储器组件的可维护性。

3. 发明申请

WO2013089685A1 ENHANCED SYSTEM SLEEP STATE SUPPORT IN SERVERS USING NON-VOLATILE RANDOM ACCESS MEMORY 审中-公开
标题翻译：使用非易失性随机访问存储器的服务器中的增强系统休眠状态支持
公开(公告)号：WO2013089685A1
公开(公告)日：2013-06-20
申请号：PCT/US2011/064686
申请日：2011-12-13
申请人： INTEL CORPORATION , KUMAR, Mohan J. , NACHIMUTHU, Murugasamy K.
发明人： KUMAR, Mohan J. , NACHIMUTHU, Murugasamy K.
IPC分类号： G06F1/32 , G06F9/06
CPC分类号： G06F1/3206 , G06F1/3275 , G06F1/3287 , G06F9/4418 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来增强对睡眠状态的支持。计算机系统包括处理器，可字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）和电源管理（PM）模块。动态随机存取存储器（DRAM）提供系统地址空间的一部分。 PM模块拦截由操作系统启动进入休眠状态的请求，将数据从DRAM复制到NVRAM，将系统地址空间的一部分映射到NVRAM，并将DRAM转换为睡眠状态。在发生唤醒事件时，PM模块向操作系统返回控制，使得计算机系统恢复工作状态操作，而操作系统不知道系统地址空间的一部分已经映射到NVRAM。

4. 发明申请

WO2011081840A2 DYNAMIC SYSTEM RECONFIGURATION 审中-公开
标题翻译：动态系统重新配置
公开(公告)号：WO2011081840A2
公开(公告)日：2011-07-07
申请号：PCT/US2010/059815
申请日：2010-12-10
申请人： INTEL CORPORATION , NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J. , WANG, Chung-Chi
发明人： NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J. , WANG, Chung-Chi
IPC分类号： G06F15/177
CPC分类号： G06F15/7871
摘要： In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached system reconfiguration code and data in order to dynamically reconfigure the hardware. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，被用来执行包括多个处理器核心的系统的动态硬件重新配置的系统重新配置代码和数据被高速缓存，并且防止了在动态硬件重新配置期间的任何直接或间接存储器访问。其中一个处理器内核执行高速缓存的系统重新配置代码和数据，以动态重新配置硬件。描述并要求保护其他实施例。

5. 发明申请

WO2013095559A1 POWER CONSERVATION BY WAY OF MEMORY CHANNEL SHUTDOWN 审中-公开
标题翻译：通过记忆通道切断的方式进行功率保存
公开(公告)号：WO2013095559A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067007
申请日：2011-12-22
申请人： INTEL CORPORATION , NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J.
发明人： NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J.
IPC分类号： G06F12/08
CPC分类号： G06F1/3275 , G06F3/061 , G06F3/0625 , G06F3/0647 , G06F3/0685 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0888 , G06F12/1027 , G06F2212/1028 , G06F2212/1044 , G06F2212/2024 , G06F2212/205 , G06F2212/60 , Y02D10/13 , Y02D10/14
摘要： A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.
摘要翻译：描述了一种方法，其包括决定进入较低功率状态，以及关闭计算机系统中的存储器通道，响应其中计算机系统中的其他存储器通道保持活动，使得计算机在存储器通道关闭时保持工作。

6. 发明申请

WO2013048406A1 METHOD AND APPARATUS FOR INJECTING ERRORS INTO MEMORY 审中-公开
标题翻译：将错误注入记忆的方法和装置
公开(公告)号：WO2013048406A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/053956
申请日：2011-09-29
申请人： INTEL CORPORATION , YIGZAW, Theodros , CHENG, Kai , KUMAR, Mohan J. , VARGAS, Jose A. , JANDHYALA, Gopikrishna
发明人： YIGZAW, Theodros , CHENG, Kai , KUMAR, Mohan J. , VARGAS, Jose A. , JANDHYALA, Gopikrishna
IPC分类号： G06F11/22 , G06F11/36 , G06F13/14
CPC分类号： G06F11/263 , G06F11/3664 , G06F11/3688
摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
摘要翻译：公开了一种向存储器注入错误的装置和方法。在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

7. 发明申请

WO2013095477A1 APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS 审中-公开
标题翻译：用于从数据触发错误中检测和恢复的装置和方法
公开(公告)号：WO2013095477A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066683
申请日：2011-12-22
申请人： INTEL CORPORATION , YIGZAW, Theodros , SANTHANAKRISHNAN, Geeyarpuram N. , SRINIVASA, Ganapati N. , VARGAS, Jose A. , SHAFI, Hisham , MISHAELI, Michael , COHEN, Ehud , SPERBER, Zeev , RAIKIN, Shlomo , KUMAR, Mohan J. , MANDELBLAT, Julius Y.
发明人： YIGZAW, Theodros , SANTHANAKRISHNAN, Geeyarpuram N. , SRINIVASA, Ganapati N. , VARGAS, Jose A. , SHAFI, Hisham , MISHAELI, Michael , COHEN, Ehud , SPERBER, Zeev , RAIKIN, Shlomo , KUMAR, Mohan J. , MANDELBLAT, Julius Y.
IPC分类号： G06F11/08 , G06F11/10
CPC分类号： G06F11/1405 , G06F11/1064
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
摘要翻译：描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保错误不会在退休阶段内破坏处理器核心的体系结构状态。

8. 发明申请

WO2015099730A1 SHARING MEMORY AND I/O SERVICES BETWEEN NODES 审中-公开
标题翻译：共享内存和NODES之间的I / O服务
公开(公告)号：WO2015099730A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077785
申请日：2013-12-26
申请人： INTEL CORPORATION , DAS SHARMA, Debendra , BLANKENSHIP, Robert G. , CHITTOR, Suresh S. , CRETA, Kenneth C. , FLEISCHER, Balint , JEN, Michelle C. , KUMAR, Mohan J. , MORRIS, Brian S.
发明人： DAS SHARMA, Debendra , BLANKENSHIP, Robert G. , CHITTOR, Suresh S. , CRETA, Kenneth C. , FLEISCHER, Balint , JEN, Michelle C. , KUMAR, Mohan J. , MORRIS, Brian S.
IPC分类号： G06F13/14 , G06F13/20 , G06F12/00
CPC分类号： G06F13/1663 , G06F12/1475 , G06F13/385 , G06F13/4282 , G06F2212/1052 , G06F2213/0026 , Y02D10/14 , Y02D10/151
摘要： A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.
摘要翻译：共享存储器控制器是通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。要允许多个独立节点中的每一个访问共享存储器资源的相应部分。在数据链路上发送互连协议数据和存储器访问协议数据，并且可以定义和识别互连协议数据和存储器访问协议数据之间的转换。

9. 发明申请

WO2014158603A1 SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS 审中-公开
标题翻译：多核处理器的系统管理中断处理
公开(公告)号：WO2014158603A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/018664
申请日：2014-02-26
申请人： INTEL CORPORATION , JAYAKUMAR, Sarathy , KUMAR, Mohan J. , KINNEY, Michael D.
发明人： JAYAKUMAR, Sarathy , KUMAR, Mohan J. , KINNEY, Michael D.
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/4812 , G06F11/0772
摘要： Technologies for system management interrupt ("SMI") handling include a number of processor cores configured to enter a system management mode ("SMM") in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.
摘要翻译：用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。其他处理器核心执行从属SMI处理程序。主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。描述和要求保护其他实施例。

10. 发明申请

WO2014098989A1 MEMORY ALLOCATION FOR VIRTUAL MACHINES USING MEMORY MAP 审中-公开
标题翻译：使用存储器映射的虚拟机的内存分配
公开(公告)号：WO2014098989A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/046885
申请日：2013-06-20
申请人： INTEL CORPORATION , CHAHAL, Sudip S. , KUMAR, Mohan J. , MEYERS, Don G. , STANASOLOVICH, David , BOELTER, Joshua
发明人： CHAHAL, Sudip S. , KUMAR, Mohan J. , MEYERS, Don G. , STANASOLOVICH, David , BOELTER, Joshua
IPC分类号： G06F12/02 , G06F9/50
CPC分类号： G06F9/45533 , G06F9/45558 , G06F9/50 , G06F9/5016 , G06F12/06 , G06F2009/45583 , G06F2212/152
摘要： Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality of memory modules; and a memory controller configured to provide a layout of the memory modules. The apparatus may further include a VMM configured to be operated by the processor to manage execution of a VM by the processor including selective allocation of the memory modules to the VM using the layout of the memory modules provided to the VMM by the memory controller. Other embodiments may be described and claimed.
摘要翻译：公开了与虚拟机的存储器分配相关联的装置和方法。在实施例中，装置可以包括处理器; 多个存储器模块; 以及存储器控制器，被配置为提供所述存储器模块的布局。该设备可以进一步包括被配置为由处理器操作以管理由处理器执行VM的VMM，包括使用由存储器控制器提供给VMM的存储器模块的布局来将存储器模块选择性地分配给VM。可以描述和要求保护其他实施例。

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