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1. 发明申请

WO2006122990A2 APARATO, SISTEMA Y MÉTODO DE DISPOSITIVO DE MEMORIA PARA CONJUNTOS MÚLTIPLES DE INSTRUCCIONES DE TIPO ESPECULATIVO 审中-公开
标题翻译：存储部署设备，多种参数类型指令的系统和方法
公开(公告)号：WO2006122990A2
公开(公告)日：2006-11-23
申请号：PCT/ES2005/000279
申请日：2005-05-19
申请人： INTEL CORPORATION , MADRILES, Carlos , RUNDBERG, Peter , SANCHEZ, Jesus , GARCIA, Carlos , MARCUELLO, Pedro , GONZÁLEZ, Antonio
发明人： MADRILES, Carlos , RUNDBERG, Peter , SANCHEZ, Jesus , GARCIA, Carlos , MARCUELLO, Pedro , GONZÁLEZ, Antonio
CPC分类号： G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： Las realizaciones de la presente invención dan a conocer una configuración de memoria multiversión que tiene la capacidad para mantener múltiples valores por conjunto de instrucciones especulativo para la misma posición de memoria para soportar precálculo y ejecución vivos del cuerpo del conjunto de instrucciones de un conjunto de instrucciones especulativo. Además, las realizaciones de la presente invención dan a conocer la validación de los valores de entrada que pueden ser calculados y utilizados en la ejecución del conjunto de instrucciones especulativo. Las realizaciones de la presente invención dan a conocer además un método para el funcionamiento de la misma.
摘要翻译：本发明涉及一种多维度存储配置，其可以为每个用于一个存储位置的每个推测的指令集存储多个值，以便能够从推测性指令集中实时预先计算和执行该组指令的正文。本发明还涉及可以在推测指令集的执行中计算和使用的输入值的验证。本发明还涉及一种执行所述验证步骤的方法。

2. 发明申请

WO2013101119A1 METHOD AND APPARATUS FOR CONTROLLING A MXCSR 审中-公开
标题翻译：用于控制MXCSR的方法和装置
公开(公告)号：WO2013101119A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067957
申请日：2011-12-29
申请人： INTEL CORPORATION , MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
发明人： MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
IPC分类号： G06F15/76 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.
摘要翻译：公开了一种通常涉及控制多媒体扩展控制和状态寄存器（MXCSR）的装置和方法。处理器核心可以包括用于执行算术功能的浮点单元（FPU）以及为FPU提供控制位的多媒体扩展控制寄存器（MXCR）。此外，优化器可以用于从多个SPEC_MXSR中选择推测性多媒体扩展状态寄存器（SPEC_MXSR），以基于指令来更新多媒体扩展状态寄存器（MXSR）。

3. 发明申请

WO2013101079A1 PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY 审中-公开
标题翻译：根据代码区域格式的软件执行情况分析异常事件
公开(公告)号：WO2013101079A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067866
申请日：2011-12-29
申请人： INTEL CORPORATION , MARTINEZ, Raul , GIBERT CODINA, Enric , LOPEZ, Pedro , TORRENTS LAPUERTA, Marti , XEKALAKIS, Polychronis , TOURNAVITIS, Georgios , STAVROU, Kyriakos, A. , PAVLOU, Demos , ORTEGA, Daniel , MARTINEZ VICENTE, Alejandro , MARCUELLO, Pedro , MAGKLIS, Grigorios , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LUPON, Marc , MADRILES, Carlos
发明人： MARTINEZ, Raul , GIBERT CODINA, Enric , LOPEZ, Pedro , TORRENTS LAPUERTA, Marti , XEKALAKIS, Polychronis , TOURNAVITIS, Georgios , STAVROU, Kyriakos, A. , PAVLOU, Demos , ORTEGA, Daniel , MARTINEZ VICENTE, Alejandro , MARCUELLO, Pedro , MAGKLIS, Grigorios , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LUPON, Marc , MADRILES, Carlos
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F11/3037 , G06F11/3409 , G06F11/3466 , G06F12/0862 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
摘要翻译：硬件和软件的组合以代码区域粒度收集用于异步事件的简档数据。示例性实施例涉及收集在本质上是异步的预取事件的度量。使用几种替代技术之一来标识属于代码区域的指令，使得为指令设置配置文件位作为标记。预取数据块的每一行都被类似地标记。然后识别与正在收集并且由代码区域内的指令产生的简档数据相对应的事件。每次识别出不同类型的事件之一时，相应的计数器将被递增。在代码区域中执行指令之后，收集在计数器中累积的简档数据，并且重置计数器以与新的代码区域一起使用。

4. 发明申请

WO2013101121A1 MANAGED INSTRUCTION CACHE PREFETCHING 审中-公开
标题翻译：管理指令高速缓存
公开(公告)号：WO2013101121A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067964
申请日：2011-12-29
申请人： INTEL CORPORATION , STAVROU, Kyriakos A. , GIBERT CODINA, Enric , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ VICENTE, Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： STAVROU, Kyriakos A. , GIBERT CODINA, Enric , CODINA, Josep M. , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ VICENTE, Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/3017 , G06F9/3802 , G06F9/3806 , G06F9/3848 , G06F12/0862 , G06F2212/452
摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
摘要翻译：公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。动态优化器可用于控制：识别公共指令高速缓存未命中并将预取引擎的预取指令插入指令高速缓存。

5. 发明申请

WO2013101078A1 SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA 审中-公开
标题翻译：支持没有数据的定量所有权
公开(公告)号：WO2013101078A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067865
申请日：2011-12-29
申请人： INTEL CORPORATION , CONDIN, Enric, Gibert , LATORRE, Fernando , CODINA, Josep, M. , REQUENA, Crispin, Gomez , GONZALEZ, Antonio , HYUSEINOVA, Mirem, (meyrem) , KOTSELIDIS, Christos, E. , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ, Vicente Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos, A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： CONDIN, Enric, Gibert , LATORRE, Fernando , CODINA, Josep, M. , REQUENA, Crispin, Gomez , GONZALEZ, Antonio , HYUSEINOVA, Mirem, (meyrem) , KOTSELIDIS, Christos, E. , LOPEZ, Pedro , LUPON, Marc , MADRILES, Carlos , MAGKLIS, Grigorios , MARCUELLO, Pedro , MARTINEZ, Vicente Alejandro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos, A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/06 , G06F12/08
CPC分类号： G06F12/0815 , G06F2212/507
摘要： Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.
摘要翻译：描述了用于为多核处理器提供增强高速缓存一致性协议的技术，其包括针对高速缓存存储器的一部分的无数据所有权的推测请求（SRFOWD）。使用SRFOWD，只有确认消息可以作为对请求核心的答案提供。受影响的缓存行的内容不需要成为答案的一部分。增强的高速缓存一致性协议可以确保在请求核心的错误推测的情况下存在当前高速缓存行的有效副本。因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。如果请求核心的推测结果是正确的，那么高速缓存行的旧内容可能会被丢弃。否则，在发出请求核心的错误猜测的情况下，高速缓存行的旧内容可能会回到有效状态。

6. 发明申请

WO2007138124A1 MÉTODO APARATO Y SISTEMA APLICADO EN UN PROTOCOLO DE COHERENCIA DE UNA MEMORIA CACHE 审中-公开
标题翻译：方法，装置和系统应用于缓存存储器协调协议
公开(公告)号：WO2007138124A1
公开(公告)日：2007-12-06
申请号：PCT/ES2006/070074
申请日：2006-05-30
申请人： INTEL CORPORATION , MADRILES GIMENO, Carlos , GARCIA QUIÑONES, Carlos , MARCUELLO, Pedro , SANCHEZ, Jesús , LATORRE, Fernando , GONZALEZ, Antonio
发明人： MADRILES GIMENO, Carlos , GARCIA QUIÑONES, Carlos , MARCUELLO, Pedro , SANCHEZ, Jesús , LATORRE, Fernando , GONZALEZ, Antonio
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： En una realización, el presente invento incluye un método para recibir un mensaje de bus en una primera memoria cache correspondiente a un acceso especulativo a una parte de una segunda memoria cache por un segundo hilo, y determinar dinámicamente en la primera memoria cache si existe una dependencia entre hilos, entre el segundo hilo y un primer hilo asociado con la primera memoria cache con respecto a esa una parte. Se describen y se reivindican otras realizaciones.
摘要翻译：在一个实施例中，本发明包括一种用于在第一高速缓冲存储器中接收总线消息的方法，所述总线消息对应于通过第二线对第二高速缓冲存储器的一部分的推测性访问，并在第一高速缓冲存储器中动态地确定是否存在依赖在第二线与第一高速缓冲存储器相关联的第一线之间的导线之间。描述和要求保护其他实施例。

7. 发明申请

WO2013095569A1 METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION 审中-公开
标题翻译：方法，选择性执行委托指令的方法和系统
公开(公告)号：WO2013095569A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067021
申请日：2011-12-22
申请人： INTEL CORPORATION , CODINA, Enric Gibert , CODINA, Josep M. , LATORRE, Fernando , MARCUELLO, Pedro , LOPEZ, Pedro , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LUPON, Marc , GIMENO, Carlos Madriles , MAGKLIS, Grigorios , VICENTE, Alejandro Martinez , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
发明人： CODINA, Enric Gibert , CODINA, Josep M. , LATORRE, Fernando , MARCUELLO, Pedro , LOPEZ, Pedro , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LUPON, Marc , GIMENO, Carlos Madriles , MAGKLIS, Grigorios , VICENTE, Alejandro Martinez , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A. , TOURNAVITIS, Georgios , XEKALAKIS, Polychronis
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30087 , G06F9/30185 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
摘要翻译：处理器确定是否执行提交动作的技术和机制。在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作。

8. 发明申请

WO2012166240A1 BRANCH PREDICTOR WITH JUMP AHEAD LOGIC TO JUMP OVER PORTIONS OF PROGRAM CODE LACKING BRANCHES 审中-公开
标题翻译：分支预测员与JUMP AHEAD逻辑跳过程序代码的缺省分支
公开(公告)号：WO2012166240A1
公开(公告)日：2012-12-06
申请号：PCT/US2012/031972
申请日：2012-04-03
申请人： INTEL CORPORATION , XEKALAKIS, Polychronis , MARCUELLO, Pedro , LATORRE, Fernando
发明人： XEKALAKIS, Polychronis , MARCUELLO, Pedro , LATORRE, Fernando
IPC分类号： G06F9/30 , G06F9/305 , G06F9/44
CPC分类号： G06F9/3867 , G06F9/30145 , G06F9/3802 , G06F9/3806 , G06F9/3844
摘要： A processor of an aspect includes front end logic to process parcels of program code. Each of the parcels has multiple instructions. A branch predictor of the processor is coupled with the front end logic. The branch predictor is to predict directions of branch instructions of the program code. The processor includes jump ahead logic to cause the branch predictor to jump over at least one parcel of the program code that does not have a branch instruction between parcels of the program code that each have at least one branch instruction.
摘要翻译：一方面的处理器包括处理程序代码的前端逻辑。每个包裹都有多个指令。处理器的分支预测器与前端逻辑相结合。分支预测器是预测程序代码的分支指令的方向。处理器包括跳转逻辑，以使分支预测器跳过至少一个程序代码的程序代码，该程序代码在程序代码的每个段都具有至少一个分支指令之间不具有分支指令。

9. 发明申请

WO2015175231A1 EXPLOITING FRAME TO FRAME COHERENCY IN A SORT-MIDDLE ARCHITECTURE 审中-公开
标题翻译：在边框中间架构中将框架与框架相结合
公开(公告)号：WO2015175231A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/028422
申请日：2015-04-30
申请人： INTEL CORPORATION
发明人： FERNANDEZ, Juan , CARRETERO CASADO, Javier , MARCUELLO, Pedro , AKENINE-MÖLLER, Tomas G.
IPC分类号： G06T11/40
CPC分类号： G06T1/20 , G06T1/60 , G06T11/40 , G06T15/005 , G06T17/10 , G06T2200/28 , G09G5/363 , G09G2330/021 , G09G2360/122
摘要： Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.
摘要翻译：在前一帧中计算的像素值可以重新用于当前帧，以分类中间架构操作。对于每个瓦片，计算并存储瓦片中使用的所有数据的哈希或其他紧凑表示，包括所有三角形，制服，纹理，着色器等。在渲染下一帧时，再次对每个图块计算出该紧凑表示。在一个中间架构中，光栅化之前就有一个自然的断点。在这个断点处，可以将紧凑表示与在同一瓦片的前一帧中计算的紧凑表示进行比较。如果这些紧凑的表示是相同的，那么就不需要为这个图块渲染任何东西。相反，彩色缓冲区或块的先前帧的其他缓冲区的内容可以被移动到当前帧的瓦片的相同缓冲器。

10. 发明公开

EP2798520A1 METHOD AND APPARATUS FOR CONTROLLING A MXCSR 审中-公开
标题翻译：方法和设备控制MXCSR
公开(公告)号：EP2798520A1
公开(公告)日：2014-11-05
申请号：EP11878906.4
申请日：2011-12-29
申请人： Intel Corporation
发明人： MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
IPC分类号： G06F15/76 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.

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