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1. 发明申请

WO2019066912A1 SELF-ALIGNED CONTACTS FOR THIN FILM TRANSISTORS 审中-公开
公开(公告)号：WO2019066912A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054368
申请日：2017-09-29
申请人： INTEL CORPORATION , LE, Van H. , SHARMA, Abhishek A. , CHU-KUNG, Benjamin , DEWEY, Gilbert , PILLARISETTY, Ravi , RESHOTKO, Miriam R. , SHIVARAMAN, Shriram , TAN, Li Huey , TRONIC, Tristan A. , KAVALIEROS, Jack T.
发明人： LE, Van H. , SHARMA, Abhishek A. , CHU-KUNG, Benjamin , DEWEY, Gilbert , PILLARISETTY, Ravi , RESHOTKO, Miriam R. , SHIVARAMAN, Shriram , TAN, Li Huey , TRONIC, Tristan A. , KAVALIEROS, Jack T.
IPC分类号： H01L29/786
CPC分类号： H01L29/78642 , H01L21/8221 , H01L27/0688 , H01L27/124 , H01L29/78648 , H01L29/78663 , H01L29/78672 , H01L29/78684 , H01L29/7869 , H01L29/78696
摘要： Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

2. 发明申请

WO2019066879A1 GROUP III-V SEMICONDUCTOR FUSES AND THEIR METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2019066879A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054185
申请日：2017-09-28
申请人： INTEL CORPORATION , THEN, Han Wui , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , TRONIC, Tristan A. , PAUL, Rajat K.
发明人： THEN, Han Wui , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , TRONIC, Tristan A. , PAUL, Rajat K.
IPC分类号： H01L23/525 , H01L23/62
摘要： Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.

3. 发明申请

WO2019005001A1 TRENCH ISOLATION PROFILE ENGINEERING FOR III-N DEVICE COMPONENTS 审中-公开
公开(公告)号：WO2019005001A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/039365
申请日：2017-06-27
申请人： INTEL CORPORATION
发明人： RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui , TRONIC, Tristan A. , FISCHER, Paul B.
IPC分类号： H01L21/768 , H01L21/762
摘要： Disclosed herein are device assemblies implementing trench isolation with modified profiles. An exemplary device assembly includes a III-N channel material and comprises a first region with a first III-N device component, a second region with a second III-N device component, and a trench therebetween. The trench has a first depth at a first area and a second depth at a second area, where the first area is closer to the first region than the second area, and the first depth is greater than the second depth. Providing different depths in a trench that isolates two adjacent III-N device regions, in particular making the trench deeper in areas of the trench which are closest to the respective III-N device regions and making it shallower in the middle, may reduce current leakage between adjacent III-N devices (i.e. improve isolation) while, at the same time, advantageously preserving relatively shallow trench profile.

4. 发明申请

WO2018212777A1 PROFILE ENGINEERING OF III-N TRANSISTORS TO REDUCE CONTACT RESISTANCE TO 2DEG 审中-公开
公开(公告)号：WO2018212777A1
公开(公告)日：2018-11-22
申请号：PCT/US2017/033439
申请日：2017-05-19
申请人： INTEL CORPORATION
发明人： RADOSAVLJEVIC, Marko , THEN, Han Wui , DASGUPTA, Sansaptak , TRONIC, Tristan A. , FISCHER, Paul B.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7786 , H01L29/0657 , H01L29/0847 , H01L29/2003 , H01L29/66 , H01L29/66462 , H01L29/66522 , H01L29/66636
摘要： Disclosed herein are transistor devices/arrangements which use III-N semiconductor material(s) as a channel material (e.g. GaN transistors) and incorporate an undercut profile in the channel material bordering source/drain (S/D) etch-out regions. Due to the undercut profile of the channel material in the S/D etch-out regions, during the subsequent epitaxial growth of the doped semiconductor material to form future S/D regions of a transistor, monocrystalline form of the epitaxially grown doped semiconductor can wrap around the ledge(s) of the channel material and make contact to the two-dimensional electron gas (2DEG) of the III-N channel material, inhibiting growth of polycrystalline doped semiconductor which has inferior conductivity compared to the same doped semiconductor in its monocrystalline form. As a result, contact resistance to the 2DEG in the channel material may be decreased, thus improving performance of III-N transistors.

5. 发明申请

WO2018030977A1 JOSEPHSON JUNCTIONS FORMED BY PARTIALLY SUBTRACTIVE FABRICATION 审中-公开
标题翻译：约瑟夫森通过部分减法制造形成的结
公开(公告)号：WO2018030977A1
公开(公告)日：2018-02-15
申请号：PCT/US2016/045941
申请日：2016-08-08
申请人： INTEL CORPORATION
发明人： YOSCOVITS, Zachary R. , CAUDILLO, Roman , CLARKE, James S. , TRONIC, Tristan A.
IPC分类号： H01L39/02 , H01L39/24 , H01L29/66 , H01L29/12
摘要： Described herein are structures that include Josephson Junctions (JJs) to be used in quantum circuits. An exemplary method for fabricating JJs includes providing a stack of a base superconductive (SC) wire layer, a junction base SC layer, and a junction tunnel barrier layer, and providing an opening through the stack. The method also includes filling the opening with a sacrificial material, and providing a top SC wire layer patterned to form a bridge over the opening and a window for removal of the sacrificial material under the bridge. The method further includes patterning the stack to form the JJ and an interconnect portion, separated from one another by the opening, and removing the sacrificial material through the window to provide a gap between the JJ and the interconnect portion. Such a method advantageously allows producing high performance JJs and can be efficiently used in large-scale manufacturing.
摘要翻译：这里描述的是包括要在量子电路中使用的约瑟夫森结（JJ）的结构。用于制造JJ的示例性方法包括提供基极超导（SC）导线层，结基SC层和结隧道势垒层的堆叠，并提供穿过堆叠的开口。该方法还包括用牺牲材料填充开口，并且提供图案化以形成开口上的桥的顶部SC线层以及用于去除桥下的牺牲材料的窗口。该方法进一步包括图案化堆叠以形成由开口彼此分开的JJ和互连部分，并且通过窗口移除牺牲材料以在JJ和互连部分之间提供间隙。这种方法有利地允许生产高性能JJ，并且可以有效地用于大规模生产。

6. 发明申请

WO2022093430A1 SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2022093430A1
公开(公告)日：2022-05-05
申请号：PCT/US2021/051146
申请日：2021-09-20
申请人： INTEL CORPORATION
发明人： LIN, Kevin , SATO, Noriyuki , TRONIC, Tristan A. , CHRISTENSON, Michael , JEZEWSKI, Christopher J. , CHEN, Jiun-Ruey , BLACKWELL, James , METZ, Matthew V. , RESHOTKO, Miriam , KABIR, Nafees , BIELEFELD, Jeffery , CHANDHOK, Manish , YOO, Hui Jae , KARPOV, Elijah V. , NAYLOR, Carl , CHEBIAM, Ramanan V.
IPC分类号： H01L27/06 , H01L27/02 , H01L21/8234 , H01L23/528 , H01L23/538
摘要： IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

7. 发明申请

WO2019132928A1 GROUP III-NITRIDE (III-N) LOGIC AND RF DEVICES AND THEIR METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2019132928A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068759
申请日：2017-12-28
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , TRONIC, Tristan A.
IPC分类号： H01L29/78 , H01L29/66
摘要： A device including a first fin structure and an adjacent second fin structure. Each fin structure includes III-Nitride (III-N) channel material and a III-N polarization charge inducing layer. The device further includes gate structures above the polarization charge inducing layers and on a portion of sidewalls of the first fin structures. The device further includes a pair of source and drain structures on opposite sides of the gate structures.

8. 发明申请

WO2019066961A1 MULTI-LAYER CRYSTALLINE BACK GATED THIN FILM TRANSISTOR 审中-公开
公开(公告)号：WO2019066961A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054589
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： LE, Van H. , SHARMA, Abhishek A. , DEWEY, Gilbert , MILLARD, Kent , KAVALIEROS, Jack , SHIVARAMAN, Shriram , TRONIC, Tristan A. , GARDNER, Sanaz , WEBER, Justin R. , GHANI, Tahir , TAN, Li Huey , LIN, Kevin
IPC分类号： H01L27/108
摘要： Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

9. 发明公开

EP3688799A1 GROUP III-V SEMICONDUCTOR FUSES AND THEIR METHODS OF FABRICATION 审中-公开
公开(公告)号：EP3688799A1
公开(公告)日：2020-08-05
申请号：EP17926938.6
申请日：2017-09-28
申请人： INTEL Corporation
发明人： THEN, Han Wui , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , TRONIC, Tristan A. , PAUL, Rajat K.
IPC分类号： H01L23/525 , H01L23/62

10. 发明公开

EP4149231A1 STACKED MEMORY STRUCTURE WITH DUAL-CHANNEL TRANSISTOR 审中-实审
公开(公告)号：EP4149231A1
公开(公告)日：2023-03-15
申请号：EP22190238.0
申请日：2022-08-12
申请人： INTEL Corporation
发明人： MA, Sean T. , SHARMA, Abhishek Anil , LILAK, Aaron D. , YOO, Hui Jae , CLENDENNING, Scott B. , LE, Van H. , TRONIC, Tristan A. , ALAAN, Urusa
IPC分类号： H10B12/00
摘要： A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

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