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    • 3. 发明申请
    • METHODS AND APPARATUS FOR REDUCING MEMORY LATENCY IN A SOFTWARE APPLICATION
    • 在软件应用中减少存储器延迟的方法和装置
    • WO2005033926A2
    • 2005-04-14
    • PCT/US2004/032212
    • 2004-09-29
    • INTEL CORPORATION
    • TIAN, XinminLIAO, Shih-WeiWANG, HongGIRKAR, MilindSHEN, JohnWANG, PerryHAAB, GrantHOFLEHNER, GerolfLAVERY, DanielSAITO, HidekiSHAH, SanjivKIM, Dongkeun
    • G06F9/30
    • G06F9/3851G06F8/4442G06F9/383G06F9/4843G06F9/52
    • Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.
    • 公开了一种用于减少软件应用中的存储器延迟的方法和装置。 所公开的系统使用一个或多个辅助线程来预取主线程的变量,以减少由于存储器延迟和/或高速缓存未命中引起的性能瓶颈。 使用性能分析工具来描述软件应用程序的资源使用情况,并识别遇到性能瓶颈的软件应用程序中的区域。 编译器运行时指令生成到软件应用程序中以创建和管理辅助线程。 辅助线程预取了遇到性能瓶颈的软件应用程序的已识别区域中的数据。 计数机制被插入到辅助线程中,并且计数机制被插入到主线程中以协调辅助线程与主线程的执行,并且有助于确保在主线程可用之前预取数据不被从高速缓存中移除 以利用预取的数据。