专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1997008882A1 VOICE ACTIVITY DETECTOR FOR HALF-DUPLEX AUDIO COMMUNICATION SYSTEM 审中-公开
标题翻译：双向音频通信系统的语音活动检测器
公开(公告)号：WO1997008882A1
公开(公告)日：1997-03-06
申请号：PCT/US1996012028
申请日：1996-07-22
申请人： INTEL CORPORATION , GRAUMANN, David, L.
发明人： INTEL CORPORATION
IPC分类号： H04M09/08
CPC分类号： H04M9/08 , G10L25/78 , H04M9/10
摘要： A method (501, 502) of detecting voice in an audio signal comprises the steps of determining an average peak value (703, AP) representing an envelope of the audio signal, determining a running instance of audio signal standard deviation (702), which corresponds to one of a number of overlapping time intervals, and updating a power density function (PDF) by adding instances of noise to the PDF if the average peak of the audio signal exceeds the current level of the audio signal by a certain amount and if the current standard deviation value falls below a threshold for a predetermined time interval. A noise floor (NF) is located based on the mean value of the PDF (501), and, if the audio signal sustains a power level exceeding the noise floor, voice activity is determined to be present in the audio signal (502). The PDF is updated by a low confidence factor (1206) if all of the standard deviation values calculated during a certain period of time are below the threshold value and by a high confidence factor (1204) if all standard deviation values within a certain longer period of time period are below the threshold value.
摘要翻译：检测音频信号中的声音的方法（501,502）包括以下步骤：确定表示音频信号的包络的平均峰值（703，AP），确定音频信号标准偏差的运行实例（702），其中对应于多个重叠时间间隔中的一个，并且如果音频信号的平均峰值超过音频信号的当前电平一定量，则通过向PDF添加噪声实例来更新功率密度函数（PDF），并且如果当前标准偏差值在预定时间间隔内下降到阈值以下。基于所述PDF（501）的平均值来设置噪声基底（NF），并且如果所述音频信号维持超过所述噪声本底的功率电平，则确定音频信号（502）中存在话音活动。如果在一定时间段内计算的所有标准偏差值都低于阈值，并且通过高置信因子（1204），则在较长时间内的所有标准差值都将通过低置信因子（1206）更新PDF 的时间段低于阈值。

2. 发明申请

WO1999034270A1 DC POWER BUS VOLTAGE TRANSIENT SUPPRESSION CIRCUIT 审中-公开
标题翻译：直流电源总线电压瞬态抑制电路
公开(公告)号：WO1999034270A1
公开(公告)日：1999-07-08
申请号：PCT/US1997024026
申请日：1997-12-29
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MASSIE, Harold, L.
IPC分类号： G05F03/02
CPC分类号： H02H3/243 , Y10T307/735
摘要： A transient suppression circuit suppresses transients on a dc power bus (15), extending between a power supply (11) and a load (14) which carries a first voltage having a nominal value, by charging a capacitor (33) to a second voltage greater than the nominal voltage, detecting a threshold at which the first voltage drops below its nominal value by more than a first predetermined amount and coupling energy from the capacitor to the bus (15) to compensate for the drop in voltage in response to detecting the threshold.
摘要翻译：瞬态抑制电路通过将电容器（33）充电到第二电压来抑制在电源（11）和承载具有标称值的第一电压的负载（14）之间延伸的直流电源总线（15）上的瞬变大于标称电压，检测第一电压低于其标称值超过第一预定量的阈值，并将来自电容器的能量耦合到总线（15），以补偿响应于检测到的电压的下降阈。

3. 发明申请

WO1998032063A2 METHOD AND APPARATUS FOR ZERO LATENCY BUS TRANSACTIONS 审中-公开
标题翻译：零延迟总线交易的方法和装置
公开(公告)号：WO1998032063A2
公开(公告)日：1998-07-23
申请号：PCT/US1997022147
申请日：1997-12-03
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , JAYAKUMAR, Muthurajan , HUANG, Sunny, C. , MACWILLIAMS, Peter, D. , WU, William, S. , PAWLOWSKI, Stephen , PRASAD, Bindi, A.
IPC分类号： G06F00/00
CPC分类号： G06F13/37 , G06F13/4252
摘要： A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.
摘要翻译：计算机系统中的分流事务总线，其允许使用附加总线以流水线方式进行无序回复以用于响应阶段。

4. 发明申请

WO1998029949A1 SINGLE-PHASE DOMINO TIME BORROWING LOGIC WITH CLOCKS AT FIRST AND LAST STAGES AND LATCH AT LAST STAGE 审中-公开
标题翻译：单相多米诺时间在最后一段和最后阶段和时间段内锁定逻辑
公开(公告)号：WO1998029949A1
公开(公告)日：1998-07-09
申请号：PCT/US1997023372
申请日：1997-12-17
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , FLETCHER, Thomas, D.
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A domino logic circuit configuration including self-timed resets (752), a pulsed clock input terminal in a first stage (712), a self-terminating pulsed clock precharge circuit in a second stage (730) which also has a pulsed clock input terminal, and a full-keeper (734, 736) in the second stage, provides time borrowing capability and reduced sensitivity to clock jitter in high frequency designs. In an embodiment, both the evaluate of the first domino stage (718) of a block and the self-terminating precharge of the last domino stage (746) of the block are initiated by the rising edge of a pulsed clock (702). In a circuit configuration in accordance with the present invention, a time period approximately equivalent to three inverter delays is provided to turn off the inputs to a subsequent domino logic stage, thus providing adequate time to evaluate the first domino logic stage in each block.
摘要翻译：包括自定时复位（752），第一级中的脉冲时钟输入端（712），第二级（730）中的自终止脉冲时钟预充电电路的多米诺逻辑电路配置，其还具有脉冲时钟输入端，以及第二阶段的全员（734,736），提供了时间借用能力，降低了高频设计中时钟抖动的灵敏度。在一个实施例中，块的第一多米诺舞台（718）的评估和块的最后多米诺舞台（746）的自终止预充电由脉冲时钟（702）的上升沿启动。在根据本发明的电路配置中，提供了大约相当于三个逆变器延迟的时间段，以将输入关断到随后的多米诺逻辑级，从而提供足够的时间来评估每个块中的第一多米诺逻辑级。

5. 发明申请

WO1998029816A1 METHOD AND APPARATUS FOR COMBINING A VOLATILE AND A NONVOLATILE MEMORY ARRAY 审中-公开
标题翻译：用于组合挥发性和非易失性存储器阵列的方法和装置
公开(公告)号：WO1998029816A1
公开(公告)日：1998-07-09
申请号：PCT/US1997018425
申请日：1997-10-14
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , PASHLEY, Richard, D. , WINSTON, Mark, D. , JUNGROTH, Owen, W. , KAPLAN, David, J.
IPC分类号： G06F13/00
CPC分类号： G11C11/005
摘要： An integrated circuit (IC) memory device (100) and method for interfacing volatile and non volatile memory arrays formed on a single semiconductor substrate. Data to be written from an external device such as a processor (104) is initially written to a volatile random access memory (RAM) write buffer array (101), and then written from the volatile RAM array (101) to a nonvolatile flash array (103) via an interface (102) to provide nonvolatile data storage at speeds typical of a RAM device. Data from first and second block addresses in the arrays may be merged in a flash merge buffer, and validity bits may be used to ensure data coherency. Data may be simultaneously written to or read from the volatile RAM array (101) during a time in which data is being read from or written to the nonvolatile flash array (103), which may be an EPROM or EEPROM.
摘要翻译：一种集成电路（IC）存储器件（100）以及用于对形成在单个半导体衬底上的易失性和非易失性存储器阵列进行接口的方法。要从诸如处理器（104）的外部设备写入的数据被初始写入到易失性随机存取存储器（RAM）写入缓冲器阵列（101）中，然后从易失性RAM阵列（101）写入非易失性闪存阵列（103）经由接口（102），以在RAM设备的典型速度下提供非易失性数据存储。阵列中的第一和第二块地址的数据可以合并在闪存合并缓冲器中，并且可以使用有效位来确保数据一致性。在数据被读取或写入非易失性闪存阵列（103）的时间期间，数据可以被同时写入到易失性RAM阵列（101）或从易失性RAM阵列读取，所述非易失性闪存阵列（103）可以是EPROM或EEPROM。

6. 发明申请

WO1998028914A1 METHOD AND APPARATUS FOR SUPPORTING VARIABLE OVERSAMPLING RATIOS WHEN DECODING VERTICAL BLANKING INTERVAL DATA 审中-公开
标题翻译：用于在解码垂直间隔间隔数据时支持可变的超级保护比率的方法和装置
公开(公告)号：WO1998028914A1
公开(公告)日：1998-07-02
申请号：PCT/US1997023391
申请日：1997-12-16
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , CAHILL, Benjamin, M., III.
IPC分类号： H04N07/087
CPC分类号： H04N7/0352 , H04N7/035
摘要： A method and apparatus for supporting variable oversampling ratios when decoding vertical blanking interval data receives an indication of an oversampling ratio (205) being used to sample a signal received during the vertical blanking interval. The sampled signal is also received. Then, based on the indication of the oversampling ratio being used, the data embedded in the vertical blanking period is identified (225).
摘要翻译：解码垂直消隐间隔数据时用于支持可变过采样比的方法和装置接收用于采样在垂直消隐间隔期间接收到的信号的过采样比（205）的指示。也接收采样信号。然后，基于所使用的过采样比的指示，识别嵌入垂直消隐期的数据（225）。

7. 发明申请

WO1998027492A1 CACHE HIERARCHY MANAGEMENT WITH LOCALITY HINTS FOR DIFFERENT CACHE LEVELS 审中-公开
标题翻译： CACHE级别管理与不同缓存级别的本地化提示
公开(公告)号：WO1998027492A1
公开(公告)日：1998-06-25
申请号：PCT/US1997022659
申请日：1997-12-12
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MITTAL, Millind
IPC分类号： G06F12/08
CPC分类号： G06F9/30047 , G06F12/0888 , G06F12/0897
摘要： A computer system and method in which allocation of a cache memory (21a, 22a) is managed by utilizing a locality hint value (17, 18), included within an instruction (19), which controls if cache allocation is to be made. The locality value is based on spatial and/or temporal locality for a data access and may be assigned to each level of a cache hierarchy where allocation control is desired. The locality hint value may be used to identify a lowest level where management of cache allocation is desired and cache is allocated at that level and any higher level or levels. If the locality hint identifies a particular access for data as temporal or non-temporal with respect to a particular cache level, the particular access may be determined to be temporal or non-temporal with respect to the higher and lower cache levels.
摘要翻译：一种计算机系统和方法，其中通过利用包括在控制是否要进行高速缓存分配的指令（19）内的位置提示值（17,18）来管理高速缓冲存储器（21a，22a）的分配。位置值基于用于数据访问的空间和/或时间局部性，并且可以被分配给期望分配控制的高速缓存层级的每个级别。可以使用本地提示值来识别希望管理高速缓存分配的最低级别，并且在该级别和任何更高级别或级别上分配高速缓存。如果局部性提示将数据的特定访问识别为相对于特定高速缓存级别的时间或非时间，则可以将特定访问确定为相对于较高和较低高速缓存级别的时间或非时间。

8. 发明申请

WO1998026576A2 METHOD AND APPARATUS FOR TUNING CHANNELS FOR CATV AND TELEVISION APPLICATIONS 审中-公开
标题翻译：用于有线电视和电视应用的调谐通道的方法和装置
公开(公告)号：WO1998026576A2
公开(公告)日：1998-06-18
申请号：PCT/US1997022038
申请日：1997-12-09
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , DANG, Nam, V. , ADAMS, Lewis, E., III
IPC分类号： H04N00/00
CPC分类号： H04N5/4446 , H03D7/163 , H04N7/102 , H04N7/16
摘要： A method of tuning channels for television and community antenna television (CATV) devices includes the step of receiving a radio frequency input (RFI) signal having at least one carrier signal at frequency fS associated with a selected broadcast channel. The RFI signal is up-converted by m to a first intermediate frequency wherein the carrier signal is located at fS + m. The first intermediate frequency is filtered. The filtered first intermediate frequency is down-converted by n to a second intermediate frequency wherein the second intermediate frequency includes the carrier signal at fS + m - n. Additional methods for improving the reception of the selected channel include the step of varying m and n in order to avoid frequency-dependent anomalies within the pass band of the filter. For digital communications, m and n are varied in accordance with an error rate of the digital communications in order to reduce the error rate of the digital communications.
摘要翻译：用于电视和社区天线电视（CATV）设备的调谐频道的方法包括接收具有与选择的广播频道相关联的频率fS的至少一个载波信号的射频输入（RFI）信号的步骤。 RFI信号由m上变频到第一中频，其中载波信号位于fS + m。第一个中频被过滤。滤波后的第一中频由n下变频到第二中频，其中第二中频包括fS + m-n处的载波信号。用于改善所选信道的接收的附加方法包括改变m和n的步骤，以避免滤波器的通带内的频率相关异常。对于数字通信，m和n根据数字通信的错误率而变化，以便减少数字通信的错误率。

9. 发明申请

WO1998022968A1 METHOD AND APPARATUS FOR DOCKING AND UNDOCKING A NOTEBOOK COMPUTER 审中-公开
标题翻译：用于锁定和解锁笔记本计算机的方法和装置
公开(公告)号：WO1998022968A1
公开(公告)日：1998-05-28
申请号：PCT/US1997017491
申请日：1997-09-29
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , CHO, Sung-Soo , BRYANT, Diane, M. , KARDACH, James, P. , DENG, Feng
IPC分类号： H01J03/00
CPC分类号： G06F13/4081 , G06F1/1632 , Y02D10/14 , Y02D10/151
摘要： Prior art quiet docking and undocking method used an interface that was located within notebook computer (10), thus adding to the cost, complexity, weight, and power consumption of the notebook computer (10). The present invention provides for an apparatus for quiet docking of a notebook computer (10) to a docking station (11), including interface circuitry located within the docking station. The interface detects when the notebook computer (10) has been inserted within the docking station (11), and correspondingly enables a switch such that a common system bus is coupled between the notebook computer (10) and docking station (11). The interface also generates events to allow a software routine to configure the notebook computer (10) and docking station (11) without prior user intervention. The interface also includes cicuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.
摘要翻译：现有技术的安静对接和脱离方法使用位于笔记本计算机（10）内的接口，从而增加笔记本计算机（10）的成本，复杂性，重量和功率消耗。本发明提供了一种用于将笔记本计算机（10）安静地对接到对接站（11）的装置，包括位于对接站内的接口电路。接口检测笔记本电脑（10）何时插入对接站（11）内，并且相应地启用开关，使得公共系统总线耦合在笔记本计算机（10）和坞站（11）之间。界面还生成事件，以允许软件程序配置笔记本电脑（10）和扩展坞（11），无需用户干预。该接口还包括检测未停靠请求的缓存，并相应地将计算机取消停靠，使得系统总线上发生的事务不受影响。

10. 发明申请

WO1998020414A1 METHOD FOR SUPPORTING A VARIETY OF INSTRUCTION FETCH UNITS IN A PIPELINE WITH A SINGLE MICROPROCESSOR CORE 审中-公开
标题翻译：在单管微核心核心的管道中支持各种指导设备单元的方法
公开(公告)号：WO1998020414A1
公开(公告)日：1998-05-14
申请号：PCT/US1997013504
申请日：1997-07-30
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MEYER, Paul, G. , STRAZDUS, Stephen , O'CONNOR, Dennis , ADELMEYER, Thomas , HEEB, Jay , TOPPS, Avery
IPC分类号： G06F09/30
CPC分类号： G06F9/3802 , G06F9/3867
摘要： A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage (52) and a decoding stage (55). The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit (59). The instruction fetch unit (59) fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipeline is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.
摘要翻译：适用于各种指令提取单元的处理器核心。处理器核心包括多个管级，包括指令指针产生级（52）和解码级（55）。核心将下游管道运行所需的所有控制与第一阶段的指令地址进行捆绑。捆绑包在核心外部传送到指令提取单元（59）。指令获取单元（59）获取指令并将其添加到捆绑包中，然后在核心内向下流出管道之前转发捆绑包。以这种方式，引入外部管道，提供核心中的不连续管段之间的连接。此外，通过将跨越外部管道级的单个束中的控制信号和地址信息捆绑为一组，减少或消除了同步问题。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式