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1. 发明申请

WO2015099684A1 PACKAGE ON PACKAGE ARCHITECTURE AND METHOD FOR MAKING 审中-公开
标题翻译：包装架构和制作方法
公开(公告)号：WO2015099684A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077601
申请日：2013-12-23
申请人： INTEL CORPORATION , GANESAN, Sanka , GUZEK, John S. , NIMKAR, Nitesh , REINGRUBER, Klaus , MEYER, Thorsten
发明人： GANESAN, Sanka , GUZEK, John S. , NIMKAR, Nitesh , REINGRUBER, Klaus , MEYER, Thorsten
IPC分类号： H01L23/12
CPC分类号： H01L23/5226 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L23/3128 , H01L23/3171 , H01L23/49811 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/12105 , H01L2224/16225 , H01L2225/06548 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3511 , H01L2924/00
摘要： Embodiments of the present disclosure are directed to package assemblies and methods for fabricating package assemblies. In one embodiment, a package assembly includes a die at least partially embedded in a mold compound; and a through mold via (TMV). The TMV may have vertical sides or may include two different portions with varying shapes. In some instances, prefabricated via bars may be used during fabrication. Package assemblies of the present disclosure may include package-on-package (POP) interconnects having a pitch of less than 0.3 mm. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及用于制造包装组件的包装组件和方法。在一个实施例中，包装组件包括至少部分地嵌入模具化合物中的模具; 和通孔（TMV）。 TMV可以具有垂直侧面或者可以包括具有变化形状的两个不同部分。在一些情况下，可以在制造期间使用预制通孔条。本公开的封装组件可以包括具有小于0.3mm的间距的封装封装（POP）互连。可以描述和/或要求保护其他实施例。

2. 发明申请

WO2013003257A2 SECONDARY DEVICE INTEGRATION INTO CORELESS MICROELECTRONIC DEVICE PACKAGES 审中-公开
标题翻译：二次设备集成到无线微电子设备包中
公开(公告)号：WO2013003257A2
公开(公告)日：2013-01-03
申请号：PCT/US2012/043945
申请日：2012-06-25
申请人： INTEL CORPORATION , TEH, Weng Hong , GUZEK, John S.
发明人： TEH, Weng Hong , GUZEK, John S.
CPC分类号： H05K3/32 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L2221/68372 , H01L2224/32245 , H01L2224/82001 , H01L2224/82002 , H01L2224/92244 , H01L2924/01006 , H01L2924/01029 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , Y10T29/49117 , Y10T29/4913 , H01L2924/00
摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.
摘要翻译：本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。

3. 发明申请

WO2013066294A1 MULTI DIE PACKAGE STRUCTURES 审中-公开
标题翻译：多层包装结构
公开(公告)号：WO2013066294A1
公开(公告)日：2013-05-10
申请号：PCT/US2011/058598
申请日：2011-10-31
申请人： INTEL CORPORATION , TEH, Weng Hong , GUZEK, John S. , ZHONG, Shan
发明人： TEH, Weng Hong , GUZEK, John S. , ZHONG, Shan
IPC分类号： H01L23/12 , H01L25/18 , H01L23/16
CPC分类号： H01L25/0657 , H01L23/12 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/5389 , H01L25/105 , H01L2224/13147 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/73 , H01L2225/06513 , H01L2225/06548 , H01L2225/06555 , H01L2225/06575 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi chip modules), systems on chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic to memory, memory to memory, and logic to logic interface stacking assemblies.
摘要翻译：描述了封装集成电路和封装集成电路芯片的方法。公开的封装组件具有包括IC芯片的间隔件和凹陷区域。提供了建筑结构，其可以例如三维（3D）封装（或封装（SiP）或多芯片模块中的系统），片上3D封装以及混合3D绑定。本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器以及逻辑到逻辑接口堆叠组件。

4. 发明申请

WO2012061091A2 ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE 审中-公开
标题翻译：包封片，包含其的微电子封装以及制造微型电子封装的方法
公开(公告)号：WO2012061091A2
公开(公告)日：2012-05-10
申请号：PCT/US2011/057594
申请日：2011-10-25
申请人： INTEL CORPORATION , GUZEK, John S. , SANKMAN, Robert L. , ICHIKAWA, Kinya , TOMITA, Yoshihiro , KUBOTA, Jiro
发明人： GUZEK, John S. , SANKMAN, Robert L. , ICHIKAWA, Kinya , TOMITA, Yoshihiro , KUBOTA, Jiro
IPC分类号： H01L23/28 , H01L23/48 , H01L21/56
CPC分类号： H01L23/3114 , H01L23/3128 , H01L23/3185 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/12105 , H01L2225/1035 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.
摘要翻译：封装的管芯（100,401）包括具有第一表面（111），相对的第二表面（112）和中间的侧表面（113）的衬底（110,510），其中有源器件位于第一表面基质。有源器件通过由多个电绝缘层（125,525）彼此分离的多个导电层（120,520）连接。保护盖（130,530）位于衬底的第一表面之上，包含暴露在其表面（131）处的互连结构（140）。在另一个实施例中，微电子封装（200）包括具有如上所述的封装管芯（100）的封装衬底（250）。

5. 发明申请

WO2014081476A1 LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS 审中-公开
标题翻译： LOGIC DIE和嵌入在建筑层中的其他组件
公开(公告)号：WO2014081476A1
公开(公告)日：2014-05-30
申请号：PCT/US2013/048355
申请日：2013-06-27
申请人： INTEL CORPORATION , KULKARNI, Deepak V. , MORTENSEN, Russell K. , GUZEK, John S.
发明人： KULKARNI, Deepak V. , MORTENSEN, Russell K. , GUZEK, John S.
IPC分类号： H01L23/64 , H01L25/16
CPC分类号： H01L23/5389 , H01L21/4857 , H01L21/50 , H01L21/76898 , H01L23/481 , H01L23/485 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L23/5386 , H01L24/19 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L28/40 , H01L2224/0401 , H01L2224/04105 , H01L2224/16145 , H01L2224/16146 , H01L2224/73209 , H01L2224/73259 , H01L2224/81005 , H01L2224/92133 , H01L2224/92224 , H01L2225/06541 , H01L2225/06548 , H01L2924/07811 , H01L2924/12042 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
摘要翻译：本公开的实施例涉及包装组件，以及用于形成包装组件和包含包装组件的系统的方法。封装组件可以包括包括多个堆积层的衬底，例如BBUL。在各种实施例中，电路由特征可以设置在衬底的外表面上。在各种实施例中，主逻辑管芯和第二管芯或电容器可以嵌入在多个堆积层中。在各种实施例中，可以在多个积层中定义电路径，以便绕过主逻辑管芯来路由第二管芯或电容器之间的电功率或接地信号与电路径特征。

6. 发明申请

WO2011056306A2 MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：微电子封装及其制造方法
公开(公告)号：WO2011056306A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/049457
申请日：2010-09-20
申请人： INTEL CORPORATION , GUZEK, John S. , SURVAKUMAR, Mahadevan , AZIMI, Hamid R.
发明人： GUZEK, John S. , SURVAKUMAR, Mahadevan , AZIMI, Hamid R.
IPC分类号： H01L23/12 , H01L23/48 , H01L23/485
CPC分类号： H01L23/49833 , H01L22/14 , H01L22/20 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
摘要翻译：微电子封装包括具有第一表面区域（125）的第一基板（120）和具有第二表面区域（135）的第二基板（130）。第一衬底包括在第一表面（121）处具有第一节距（127）的第一组互连（126）和在第二表面（222）处具有第二节距（129）的第二组互连（128）。第二衬底使用第二组互连耦合到第一衬底并且包括具有第三节距（237）的第三组互连（236）和以微孔彼此连接的内部导电层（233,234）（ 240）。第一节距小于第二节距，第二节距小于第三节距，并且第一表面区域小于第二表面区域。

7. 发明申请

WO2015026344A1 BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) 审中-公开
标题翻译：用于无障碍建筑物层（BBUL）的无缝包装接口
公开(公告)号：WO2015026344A1
公开(公告)日：2015-02-26
申请号：PCT/US2013/056058
申请日：2013-08-21
申请人： INTEL CORPORATION , TEH, Weng Hong , GUZEK, John S. , SANKMAN, Robert L.
发明人： TEH, Weng Hong , GUZEK, John S. , SANKMAN, Robert L.
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L23/5389 , H01L21/563 , H01L21/568 , H01L23/49816 , H01L23/5386 , H01L24/19 , H01L24/97 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/8203 , H01L2224/82031 , H01L2225/1035 , H01L2225/1058 , H01L2924/10253 , H01L2924/1433 , H01L2924/18162
摘要： Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对集成电路（IC）封装组件中的嵌入式硅管芯的无扰动接口。在一个实施例中，一种方法包括在其中形成限定空腔的电介质材料的周围部分; 将至少一个模具放置在所述空腔中，所述模具包括接触件; 在模具和周围部分上沉积电介质材料; 蚀刻介电材料以暴露接触; 并将导电材料沉积到触点上。可以描述和/或要求保护其他实施例。

8. 发明申请

WO2013101242A1 BBUL TOP SIDE SUBSTRATE LAYER ENABLING DUAL SIDED SILICON INTERCONNECT AND STACKING FLEXIBILITY 审中-公开
标题翻译： BBUL顶层底板层启用双面硅互连和堆叠灵活性
公开(公告)号：WO2013101242A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068277
申请日：2011-12-31
申请人： INTEL CORPORATION , NICKERSON, Robert M. , TAO, Min , GUZEK, John S.
发明人： NICKERSON, Robert M. , TAO, Min , GUZEK, John S.
IPC分类号： H01L23/48 , H05K3/46
CPC分类号： H01L24/19 , H01L23/49822 , H01L23/49838 , H01L23/4985 , H01L23/5389 , H01L24/03 , H01L24/06 , H01L24/16 , H01L24/20 , H01L24/73 , H01L24/92 , H01L25/18 , H01L2224/0401 , H01L2224/04105 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/24225 , H01L2224/73259 , H01L2224/821 , H01L2224/92224 , H01L2224/97 , H01L2924/00013 , H01L2924/10253 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H05K1/185 , H05K1/186 , H05K3/4682 , H05K2201/10674 , H05K2203/1469 , H01L2224/81 , H01L2224/82 , H01L2224/13099 , H01L2224/05099 , H01L2224/05599 , H01L2924/00
摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.
摘要翻译：一种包括模具的设备，所述模具包括具有接触点的装置侧的第一侧和相对的第二侧; 以及堆叠载体，其包括设置在所述管芯的第一侧上的至少一层导电材料，以及设置在所述管芯的第二侧上的导电材料和介电材料的多个交替层，其中所述至少一个层在模具的第一侧上的导电材料的至少一个与模具的第二侧上的（1）至少一个导电材料的交替层中的至少一个耦合，并且（2）至少一个死。一种方法，包括邻近模具的一侧形成积聚载体的第一部分，以及与所述模具的另一侧相邻地形成所述堆积载体的第二部分。

9. 发明申请

WO2013089754A1 PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES 审中-公开
标题翻译：包装半导体套件，用于无阻堆叠接口（BBUL）包装
公开(公告)号：WO2013089754A1
公开(公告)日：2013-06-20
申请号：PCT/US2011/065269
申请日：2011-12-15
申请人： INTEL CORPORATION , MALATKAR, Pramod , TEH, Weng Hong , GUZEK, John S. , SANKMAN, Robert L.
发明人： MALATKAR, Pramod , TEH, Weng Hong , GUZEK, John S. , SANKMAN, Robert L.
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/09 , H01L23/481 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/19 , H01L24/97 , H01L27/08 , H01L2224/04105 , H01L2224/08235 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15153 , H01L2924/00 , H01L2224/83 , H01L2224/82
摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
摘要翻译：描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

10. 发明申请

WO2018004907A1 INTEGRATED CIRCUIT PACKAGE STACK 审中-公开
标题翻译：集成电路封装堆栈
公开(公告)号：WO2018004907A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/034761
申请日：2017-05-26
申请人： INTEL CORPORATION
发明人： JAYARAMAN, Saikumar , GUZEK, John S. , MEKONNEN, Yidnekachew S.
IPC分类号： H01L25/07 , H01L25/065 , H01L23/48 , H01L23/538
摘要： Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.
摘要翻译：本文公开了与集成电路（IC）封装设计相关联的设备，方法和系统。 IC封装堆叠可以包括第一IC封装和第二IC封装。第一IC封装可以包括第一管芯和第一重新分布层，其将第一IC封装的第一侧上的接触连通地耦合到第一管芯并且连接到第一IC封装的第二侧上的接触，第二侧与第一面。第二IC封装可以被安装到第一IC封装的第二侧。第二IC封装可以包括第二管芯和第二重分配层，其将第二IC封装的一侧上的接触通信地耦合到第二管芯，第二IC封装的接触通信地耦合到第一IC芯片的第一侧上的接触 IC封装。

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