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1. 发明申请

WO2017111950A1 ELECTRONIC ASSEMBLY THAT INCLUDES A BRIDGE 审中-公开
标题翻译：电子装配，包括桥梁
公开(公告)号：WO2017111950A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067418
申请日：2015-12-22
申请人： INTEL CORPORATION , DESHPANDE, Nitin , LIFF, Shawna M. , EITAN, Amram
发明人： DESHPANDE, Nitin , LIFF, Shawna M. , EITAN, Amram , LI, Eric , KARHADE, Omkar , GOSSELIN, Timothy A.
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L23/48 , H01L23/13 , H01L23/36 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L25/50 , H01L2224/0612 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81203 , H01L2224/92125 , H01L2924/15159 , H01L2924/014 , H01L2924/00014
摘要： An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.
摘要翻译：包括具有上表面的基板和包括上表面的桥的电子组件。桥位于基板上表面的空腔内。第一电子元件连接到电桥的上表面和基板的上表面，第二电子元件连接到电桥的上表面和基板的上表面，其中桥电连接第一电子元件组件连接到第二电子组件。

2. 发明申请

WO2017099788A1 MICROELECTRONIC STRUCTURES HAVING MULTIPLE MICROELECTRONIC DEVICES CONNECTED WITH A MICROELECTRONIC BRIDGE EMBEDDED IN A MICROELECTRONIC SUBSTRATE 审中-公开
标题翻译：微电子结构具有多个微电子器件与微电子基板连接在一个微电子基板中
公开(公告)号：WO2017099788A1
公开(公告)日：2017-06-15
申请号：PCT/US2015/065165
申请日：2015-12-11
申请人： INTEL CORPORATION
发明人： LI, Eric , GOSSELIN, Timothy , TOMITA, Yoshihiro , LIFF, Shawna , EITAN, Amram , SALTAS, Mark
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L23/48 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/13 , H01L23/5381 , H01L23/5385 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/96 , H01L25/0655 , H01L2224/11002 , H01L2224/1182 , H01L2224/131 , H01L2224/14134 , H01L2224/14177 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/1701 , H01L2224/1703 , H01L2224/27002 , H01L2224/3201 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73104 , H01L2224/73204 , H01L2224/81005 , H01L2224/81011 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/83005 , H01L2224/83102 , H01L2224/83104 , H01L2224/92125 , H01L2224/95 , H01L2224/95001 , H01L2224/96 , H01L2924/15153 , H01L2924/181 , H01L2924/18161 , H01L2224/14131 , H01L2224/11 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2224/27
摘要： A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
摘要翻译：微电子结构包括具有第一表面和从微电子衬底第一表面延伸到衬底中的空腔的微电子衬底，附着到微电子衬底第一表面的第一微电子器件和第二微电子器件，以及布置在微电子衬底腔内并且附着到第一微电子器件和第二微电子器件的微电子桥。在一个实施例中，微电子结构可以包括由第一微电子器件和第二微电子器件形成的重构晶片。在另一个实施例中，焊剂材料可以在第一微电子器件和微电子桥之间以及第二微电子器件和微电子桥之间延伸。

3. 发明申请

WO2017105764A1 ELECTRONIC PACKAGE THAT INCLUDES FINE POWDER COATING 审中-公开
标题翻译：电子包装，包括精细粉末涂料
公开(公告)号：WO2017105764A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/062741
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： LU, Donglai David , LI, Zhaozhi George , MAGNAVITA, Matthew T. , EITAN, Amram , CHEN, Peng
IPC分类号： H01L23/29 , H01L23/31
CPC分类号： H01L23/562 , H01L21/563 , H01L23/29 , H01L23/295 , H01L23/3121 , H01L23/3128 , H01L23/3135 , H01L23/3736 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/3511 , H01L2924/37001
摘要： An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the electronic component by melting the metal powder onto the electronic component. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the substrate by melting the metal powder onto the substrate. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; an initial mold covering the electronic component; and a porous coating that includes grains of metal powder formed onto the initial mold by melting the metal powder onto the initial mold.
摘要翻译：包括衬底的电子封装; 安装到所述基板的表面的电子部件; 以及多孔涂层，其包括通过将金属粉末熔化到电子部件上而形成在电子部件上的金属粉末的颗粒。一种电子封装，其包括衬底; 安装到所述基板的表面的电子部件; 以及多孔涂层，其包括通过将金属粉末熔化到基板上而形成在基板上的金属粉末颗粒。一种电子封装，其包括衬底; 安装到所述基板的表面的电子部件; 覆盖电子部件的初始模具; 以及多孔涂层，其包括通过将金属粉末熔化到初始模具上而在初始模具上形成的金属粉末颗粒。

4. 发明申请

WO2016204753A1 TWO MATERIAL HIGH K THERMAL ENCAPSULANT SYSTEM 审中-公开
标题翻译：两种材料高K热封装系统
公开(公告)号：WO2016204753A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036272
申请日：2015-06-17
申请人： INTEL CORPORATION
发明人： MCMAHAN, Venmathy , NAGARAJAN, Sivakumar , BOZORG-GRAYELI, Elah , MALLIK, Amrita , CHU, Kuang-Han , WANG, Liwei , ANANTHAKRISHNAN, Nisha , WEINMAN, Craig J. , EITAN, Amram
IPC分类号： H01L25/07 , H01L23/28 , H01L23/48
CPC分类号： H01L23/29 , H01L21/563 , H01L23/18 , H01L23/31 , H01L23/3737 , H01L23/48 , H01L25/07
摘要： Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.
摘要翻译：一些实施例涉及电子包装。电子封装包括第一裸片和堆叠在第一裸片上的第二裸片。第一密封剂位于第一管芯和第二管芯之间。第一密封剂包括覆盖第一管芯和第二管芯之间的第一容积的第一材料。第二密封剂位于第一管芯和第二管芯之间。第二密封剂包括覆盖第一管芯和第二管芯之间的第二容积的第二材料。第一材料具有比第二材料更高的热导率，并且与第一材料相比，第二材料更有效地促进第一模具和第二模具之间的电连接。

5. 发明公开

EP3506346A3 SUBSTRATE ASSEMBLY WITH SPACER ELEMENT 审中-实审
公开(公告)号：EP3506346A3
公开(公告)日：2019-08-21
申请号：EP18209342.7
申请日：2018-11-29
申请人： INTEL Corporation
发明人： XIE, Huxiao , EITAN, Amram , LU, Xiao
IPC分类号： H01L23/485 , H01L21/60 , H01L21/48
摘要： Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.

6. 发明公开

EP4167278A2 METHODS AND APPARATUSES WITH REDUCED DEFECTS IN INTERCONNECTING BUMPS BETWEEN A SEMICONDUCTOR DIE AND A SUBSTRATE (A PACKAGE SUBSTRATE OR ANOTHER DIE) 审中-实审
公开(公告)号：EP4167278A2
公开(公告)日：2023-04-19
申请号：EP22197135.1
申请日：2022-09-22
申请人： INTEL Corporation
发明人： MANEPALLI, Rahul N. , EITAN, Amram , Arana, Leonel , XU, Dingying , LIU, Changhua , CHO, Steve , FENG, Hongxia , HAN, Jung Kyu , GUO, Xiaoying , MC ELHINNY, Kyle
IPC分类号： H01L23/485 , H01L23/538 , H01L21/60 , H01L21/603
摘要： Example methods and apparatuses reduce the likelihood of defects forming in bumps (114, 116, 118, 808, 810) associated with first level interconnects between semiconductor dies (106, 108, 802) and substrates (package substrates (110, 804) or other dies) associated with shifting in plated tin (1802, 2506) upon stripping and swelling of a dry film resist (1002, 1102, 2406), wicking of tin (1802, 2506) upon tin (solder) reflow following removal of the dry film resist (1002, 1102, 2406) (which both could lead to unintended bridging of bumps) and a lack of co-planarity across different bumps due to warpage and/or other factors, by fabricating dummy bumps (702, 812) adjacent operational bridge bumps (604, 810), fabricating bumps (1806+1808+1802) with bases (1806+1808) with non-circular shapes (e.g., polygonal shapes such as octagonal or hexagonal, wherein the shape may correspond to a packing geometry of the bumps), and/or fabricating bumps (2502+2504+2506) with diameters or widths and heights that differ spatially across the area (e.g., between ring-shaped regions (2712)) over which the bumps (2502+2504+2506) are distributed. Such potential defects are reduced in a manner that enables the bumps to be fabricated with a smaller size and/or smaller spacing to meet the ongoing needs of scaling down the overall size of electronic components. In an embodiment, the bumps (114) of the first level interconnects include two different types of bumps corresponding to core bumps (116, 808) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between the dies (106, 108, 802) and the package substrate (110, 804) and then to components external to the IC package (100)) and bridge bumps (118, 810) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between different ones of the dies (106, 108, 802) within the package (100), via an interconnect bridge (126) embedded in the package substrate (110)), wherein the core bumps (116, 808) are typically larger than the bridge bumps (118, 810). An array of dummy bridge bumps (702, 812) may be positioned adjacent the outer edge or perimeter of the operational bridge bumps (604, 810) so as to at least partially fill in open spaces (608) adjacent an outer edge or perimeter of the array of operational bridge bumps (604, 810) and thus limit bump shifting upon resist swelling in the remaining open space to the dummy bridge bumps (702, 812), thereby protecting the operational bridge bumps (604, 810), as well as to improve plating uniformity (e.g., the relative bump thickness variation (rBTV)) across the operational bridge bumps (604, 810). The operational bridge bumps (604, 810) and the dummy bridge bumps (702, 812) may have the same or different size and shape. The dummy bridge bumps (812) may have a shorter height so that they do not form a connection that extends a full distance between the die (802) and the package substrate (804).

7. 发明公开

EP4167278A3 METHODS AND APPARATUSES WITH REDUCED DEFECTS IN INTERCONNECTING BUMPS BETWEEN A SEMICONDUCTOR DIE AND A SUBSTRATE (A PACKAGE SUBSTRATE OR ANOTHER DIE) 审中-实审
公开(公告)号：EP4167278A3
公开(公告)日：2023-06-28
申请号：EP22197135.1
申请日：2022-09-22
申请人： INTEL Corporation
发明人： MANEPALLI, Rahul N. , EITAN, Amram , Arana, Leonel , XU, Dingying , LIU, Changhua , CHO, Steve , FENG, Hongxia , HAN, Jung Kyu , GUO, Xiaoying , MC ELHINNY, Kyle
IPC分类号： H01L23/485 , H01L23/538 , H01L21/60 , H01L21/603
摘要： Example methods and apparatuses reduce the likelihood of defects forming in bumps (114, 116, 118, 808, 810) associated with first level interconnects between semiconductor dies (106, 108, 802) and substrates (package substrates (110, 804) or other dies) associated with shifting in plated tin (1802, 2506) upon stripping and swelling of a dry film resist (1002, 1102, 2406), wicking of tin (1802, 2506) upon tin (solder) reflow following removal of the dry film resist (1002, 1102, 2406) (which both could lead to unintended bridging of bumps) and a lack of co-planarity across different bumps due to warpage and/or other factors, by fabricating dummy bumps (702, 812) adjacent operational bridge bumps (604, 810), fabricating bumps (1806+1808+1802) with bases (1806+1808) with non-circular shapes (e.g., polygonal shapes such as octagonal or hexagonal, wherein the shape may correspond to a packing geometry of the bumps), and/or fabricating bumps (2502+2504+2506) with diameters or widths and heights that differ spatially across the area (e.g., between ring-shaped regions (2712)) over which the bumps (2502+2504+2506) are distributed. Such potential defects are reduced in a manner that enables the bumps to be fabricated with a smaller size and/or smaller spacing to meet the ongoing needs of scaling down the overall size of electronic components. In an embodiment, the bumps (114) of the first level interconnects include two different types of bumps corresponding to core bumps (116, 808) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between the dies (106, 108, 802) and the package substrate (110, 804) and then to components external to the IC package (100)) and bridge bumps (118, 810) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between different ones of the dies (106, 108, 802) within the package (100), via an interconnect bridge (126) embedded in the package substrate (110)), wherein the core bumps (116, 808) are typically larger than the bridge bumps (118, 810). An array of dummy bridge bumps (702, 812) may be positioned adjacent the outer edge or perimeter of the operational bridge bumps (604, 810) so as to at least partially fill in open spaces (608) adjacent an outer edge or perimeter of the array of operational bridge bumps (604, 810) and thus limit bump shifting upon resist swelling in the remaining open space to the dummy bridge bumps (702, 812), thereby protecting the operational bridge bumps (604, 810), as well as to improve plating uniformity (e.g., the relative bump thickness variation (rBTV)) across the operational bridge bumps (604, 810). The operational bridge bumps (604, 810) and the dummy bridge bumps (702, 812) may have the same or different size and shape. The dummy bridge bumps (812) may have a shorter height so that they do not form a connection that extends a full distance between the die (802) and the package substrate (804).

8. 发明公开

EP3506346A2 SUBSTRATE ASSEMBLY WITH SPACER ELEMENT 审中-实审
公开(公告)号：EP3506346A2
公开(公告)日：2019-07-03
申请号：EP18209342.7
申请日：2018-11-29
申请人： INTEL Corporation
发明人： XIE, Huxiao , EITAN, Amram , LU, Xiao
IPC分类号： H01L23/485 , H01L21/60 , H01L21/48
CPC分类号： H01L24/13 , H01L24/06 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/89 , H01L2224/02233 , H01L2224/10165 , H01L2224/1132 , H01L2224/11332 , H01L2224/13023 , H01L2224/13147 , H01L2224/13155 , H01L2224/1319 , H01L2224/13211 , H01L2224/13311 , H01L2224/13347 , H01L2224/13355 , H01L2224/13411 , H01L2224/13499 , H01L2224/16237 , H01L2224/165 , H01L2224/80051 , H01L2224/80815 , H01L2224/81005 , H01L2224/8114 , H01L2224/81192 , H01L2224/81815 , H01L2924/0105 , H01L2924/014 , H01L2924/00014
摘要： Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.

9. 发明公开

EP3311408A1 TWO MATERIAL HIGH K THERMAL ENCAPSULANT SYSTEM 有权
标题翻译：两种材料高K热封装体系
公开(公告)号：EP3311408A1
公开(公告)日：2018-04-25
申请号：EP15895800.9
申请日：2015-06-17
申请人： Intel Corporation
发明人： MCMAHAN, Venmathy , NAGARAJAN, Sivakumar , BOZORG-GRAYELI, Elah , MALLIK, Amrita , CHU, Kuang-Han , WANG, Liwei , ANANTHAKRISHNAN, Nisha , WEINMAN, Craig J. , EITAN, Amram
IPC分类号： H01L25/07 , H01L23/28 , H01L23/48
CPC分类号： H01L23/29 , H01L21/563 , H01L23/18 , H01L23/31 , H01L23/3737 , H01L23/48 , H01L25/0657 , H01L25/074 , H01L2225/06572 , H01L2225/06589
摘要： Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

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