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1. 发明申请

WO2013095564A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN NUMERICAL ORDER THAT DIFFER BY A CONSTANT STRIDE 审中-公开
标题翻译：处理器，方法，系统和指令，用于生成恒定序列的数字序列中的整数序列
公开(公告)号：WO2013095564A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067014
申请日：2011-12-22
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
发明人： OULD-AHMED-VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F13/14
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by a constant stride of at least two. In an aspect, storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一方面的方法包括接收指示目的地存储位置的指令。结果存储在目的地存储位置以响应该指令。结果包括以数字顺序的至少四个非负整数的序列，其中连续位置中的所有整数与至少两个的恒定步幅相差。在一方面，使用前一条指令的结果，在不计算至少四个整数的情况下执行存储包括至少四个整数的序列的结果。公开了其它方法，装置，系统和指令。

2. 发明申请

WO2013095563A1 PACKED DATA REARRANGEMENT CONTROL INDEXES PRECURSORS GENERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译：包装数据重新布置控制指标前提条件生成处理器，方法，系统和说明
公开(公告)号：WO2013095563A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067013
申请日：2011-12-22
申请人： INTEL CORPORATION , ABRAHAM, Seth , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , SPERBER, Zeev , GRADSTEIN, Amit
发明人： ABRAHAM, Seth , VALENTINE, Robert , OULD-AHMED-VALL, Elmoustapha , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F13/14
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一方面的方法包括接收指示目的地存储位置的指令。结果存储在目的地存储位置以响应该指令。结果包括结果，包括至少四个非负整数的序列。在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。公开了其它方法，装置，系统和指令。

3. 发明申请

WO2013095555A1 PACKED DATA REARRANGEMENT CONTROL INDEXES GENERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译：包装数据重新布置控制指标生成处理器，方法，系统和说明
公开(公告)号：WO2013095555A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067000
申请日：2011-12-22
申请人： INTEL CORPORATION , OULD-AHMED VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
发明人： OULD-AHMED VALL, Elmoustapha , ABRAHAM, Seth , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F13/14
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一方面的方法包括接收打包数据重排控制索引生成指令。打包数据重排控制索引生成指令表示目的地存储位置。响应于打包数据重排控制索引生成指令，将结果存储在目的地存储位置。结果包括代表压缩数据重排控制指标的至少四个非负整数的序列。在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。公开了其它方法，装置，系统和指令。

4. 发明申请

WO2013095580A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN WHICH INTEGERS IN CONSECUTIVE POSITIONS DIFFER BY A CONSTANT INTEGER STRIDE AND WHERE A SMALLEST INTEGER IS OFFSET FROM ZERO BY AN INTEGER OFFSET 审中-公开
标题翻译：处理器，方法，系统和指令，用于生成整数的序列，其中整数位置中的整数在恒定整数的范围内不同，并且最小的整数由整数偏移从零偏移
公开(公告)号：WO2013095580A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067047
申请日：2011-12-22
申请人： INTEL CORPORATION , ABRAHAM, Seth , VALL, El Moustapha Ould-Ahmed , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
发明人： ABRAHAM, Seth , VALL, El Moustapha Ould-Ahmed , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305 , G06F13/14
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：方面的方法包括接收指令。该指令指示整数步长，表示整数偏移，并指示目的地存储位置。结果存储在目的地存储位置以响应该指令。结果包括以数字顺序的至少四个整数的序列，其中至少四个整数中的最小的整数与零与整数偏移不同，并且具有与整数步长不同的连续位置中的序列的所有整数。公开了其它方法，装置，系统和指令。

5. 发明申请

WO2013095554A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF CONSECUTIVE INTEGERS IN NUMERICAL ORDER 审中-公开
标题翻译：处理器，方法，系统和指令，用于生成数字序列中的数字整数序列
公开(公告)号：WO2013095554A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066999
申请日：2011-12-22
申请人： INTEL CORPORATION , ABRAHAM, Seth , VALL, ElMoustapha, Ould-Ahmed , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
发明人： ABRAHAM, Seth , VALL, ElMoustapha, Ould-Ahmed , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F17/10 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一方面的方法包括接收指示目的地存储位置的指令。结果存储在目的地存储位置以响应该指令。结果包括数字顺序的至少四个连续的非负整数的序列。在一方面，该指令不表示在架构可见的存储位置中具有多个打包数据元素的源打包数据操作数。公开了其它方法，装置，系统和指令。

6. 发明申请

WO2012134532A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开
标题翻译：向导友好指示格式及其执行
公开(公告)号：WO2012134532A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/054303
申请日：2011-09-30
申请人： INTEL CORPORATION , VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
发明人： VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译：一种向量友好的指令格式及其执行。根据本发明的一个实施例，处理器被配置为执行指令集。指令集包括向量友好指令格式。向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作，基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段，在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

7. 发明申请

WO2018004894A1 VIRTUALIZING PRECISE EVENT BASED SAMPLING 审中-公开
标题翻译：基于虚拟化精确事件的抽样
公开(公告)号：WO2018004894A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/034331
申请日：2017-05-24
申请人： INTEL CORPORATION
发明人： MERTEN, Matthew C. , STRONG, Beeman C. , CHYNOWETH, Michael W. , ZHOU, Grant G. , KLEEN, Andreas , WEIER, Kimberly C. , SCHMID, Angela D. , BRATANOV, Stanislav , ABRAHAM, Seth , BRANDT, Jason W. , YASIN, Ahmad
IPC分类号： G06F9/455
摘要： A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
摘要翻译：一个内核包含一个内存缓冲区并执行一个虚拟机内的指令。处理器跟踪器捕获跟踪数据并将跟踪数据格式化为跟踪数据包。作为执行指令的结果，基于事件的采样器响应于发生特定类型的事件而生成采样记录的字段数据。处理器跟踪器在接收到现场数据时：将现场数据格式化为采样记录的元素作为一组记录包; 在跟踪数据分组之间插入一组记录分组作为组合分组流; 并将组合的分组流作为一系列输出页面存储在存储缓冲器中。处于guest虚拟机分析模式时，核心执行虚拟机监视器，以使用多级页面表将内存缓冲区的输出页映射到主内存的物理页面。

8. 发明授权

EP2695054B1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 有权
公开(公告)号：EP2695054B1
公开(公告)日：2018-08-15
申请号：EP11862801.5
申请日：2011-09-30
申请人： Intel Corporation
发明人： VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

9. 发明公开

EP2695054A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 有权
标题翻译：矢量友好指令格式及其实现
公开(公告)号：EP2695054A1
公开(公告)日：2014-02-12
申请号：EP11862801.5
申请日：2011-09-30
申请人： Intel Corporation
发明人： VALENTINE, Robert, C. , SAN ADRIAN, Jesus, Corbal , SANS, Roger, Espasa , CAVIN, Robert, D. , TOLL, Bret, L. , DURAN, Santiago, Galan , WIEDEMEIER, Jeffrey, G. , SAMUDRALA, Sridhar , GIRKAR, Milind, Baburao , GROCHOWSKI, Edward, Thomas , HALL, Jonathan, Cannon , BRADFORD, Dennis, R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James, C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew, Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

10. 发明公开

EP3805921A3 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 有权
公开(公告)号：EP3805921A3
公开(公告)日：2021-06-30
申请号：EP20199439.9
申请日：2011-09-30
申请人： INTEL Corporation
发明人： VALENTINE, Robert C. , SAN ADRIAN, Jesus Corbal , SANS, Roger Espasa , CAVIN, Robert D. , TOLL, Bret L. , DURAN, Santiago Galan , WIEDEMEIER, Jeffrey G. , SAMUDRALA, Sridhar , GIRKAR, Milind Baburao , GROCHOWSKI, Edward Thomas , HALL, Jonathan Cannon , BRADFORD, Dennis R. , OULD-AHMED-VALL, Elmoustapha , ABEL, James C. , CHARNEY, Mark , ABRAHAM, Seth , SAIR, Suleyman , FORSYTH, Andrew Thomas , YOUNT, Charles , WU, Lisa
IPC分类号： G06F9/30
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

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