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1. 发明申请

WO2022132263A1 CAP STRUCTURE FOR INTERCONNECT DIELECTRICS AND METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2022132263A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/051145
申请日：2021-09-20
申请人： INTEL CORPORATION
发明人： VYAS, Shashi , NASKAR, Sudipto , WALLACE, Charles
IPC分类号： H01L21/768 , H01L21/02 , H01L23/528
摘要： An integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures, a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, the cap structure includes a top surface and a sidewall surface and a liner comprising a third dielectric on the top surface and on the sidewall surface.

2. 发明申请

WO2007109463A1 METHOD OF FORMING TRENCH CONTACTS FOR MOS TRANSISTORS 审中-公开
标题翻译：形成用于MOS晶体管的TRENCH接触的方法
公开(公告)号：WO2007109463A1
公开(公告)日：2007-09-27
申请号：PCT/US2007/063940
申请日：2007-03-14
申请人： INTEL CORPORATION , SIVAKUMAR, Swaminathan , WALLACE, Charles , DAVIS, Alison , RAHHAL-ORABI, Nadia
发明人： SIVAKUMAR, Swaminathan , WALLACE, Charles , DAVIS, Alison , RAHHAL-ORABI, Nadia
IPC分类号： H01L21/28 , H01L21/335 , H01L21/336 , H01L29/768
CPC分类号： H01L21/76808 , H01L21/76816 , H01L21/76895 , H01L23/485
摘要： A method to form transistor contacts begins with providing a transistor that includes a gate stack and first and second diffusion regions formed on a substrate, and a dielectric layer formed atop the gate stack and the diffusion regions. A first photolithography process forms first and second diffusion trench openings for the first and second diffusion regions. A sacrificial layer is then deposited into the first and second diffusion trench openings. Next, a second photolithography process forms a gate stack trench opening for the gate stack and a local interconnect trench opening coupling the gate stack trench opening to the first diffusion trench opening. The second photolithography process is carried out independent of the first photolithography process. The sacrificial layer is then removed and a metallization process is carried out to fill the first and second diffusion trench openings, the gate stack trench opening, and the local interconnect trench opening with a metal layer.
摘要翻译：形成晶体管触点的方法开始于提供一种晶体管，该晶体管包括栅极堆叠以及形成在衬底上的第一和第二扩散区域，以及形成在栅极堆叠和扩散区域顶部的电介质层。第一光刻工艺形成用于第一和第二扩散区域的第一和第二扩散沟槽开口。然后将牺牲层沉积到第一和第二扩散沟槽开口中。接下来，第二光刻工艺形成用于栅极堆叠的栅极堆叠沟槽开口和将栅极堆叠沟槽开口耦合到第一扩散沟槽开口的局部互连沟槽开口。第二光刻工艺是独立于第一光刻工艺进行的。然后去除牺牲层，并且进行金属化处理以填充第一和第二扩散沟槽开口，栅极堆叠沟槽开口和具有金属层的局部互连沟槽开口。

3. 发明公开

EP4109556A1 RELEASED FIN FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION 审中-实审
公开(公告)号：EP4109556A1
公开(公告)日：2022-12-28
申请号：EP22163378.7
申请日：2022-03-21
申请人： Intel Corporation
发明人： GHANI, Tahir , GOLONZKA, Oleg , WALLACE, Charles , GULER, Leonard
IPC分类号： H01L29/775 , H01L21/336 , H01L29/06 , H01L29/10 , B82Y10/00 , H01L29/08
摘要： Released fins (108), preferably comprising nanowires (112), for advanced integrated circuit structure fabrication, such as nanowire FETs and finFETs are described. An integrated circuit structure includes a substrate (102), a sub-fin (104), a dielectric spacer material (124) on the sub-fin and a fin (108) on the dielectric spacer material. A void (126) is present in the dielectric spacer material, vertically and laterally between the sub-fin and the fin.

4. 发明公开

EP4105979A1 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BACKSIDE REMOVAL APPROACH 审中-实审
公开(公告)号：EP4105979A1
公开(公告)日：2022-12-21
申请号：EP22166383.4
申请日：2022-04-01
申请人： INTEL Corporation
发明人： GHANI, Tahir , WALLACE, Charles , GULER, Leonard
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/775
摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a backside removal approach, are described. For example, an integrated circuit structure includes a first insulator sub-fin structure over a first stack of nanowires. A second insulator sub-fin structure is over a second stack of nanowires, the second stack of nanowires having a greater number of nanowires than the first stack of nanowires, and the second insulator sub-fin structure having a vertical thickness less than a vertical thickness of the first insulator sub-fin structure. A first gate electrode is around the first stack of nanowires, and a second gate electrode is around the second stack of nanowires.

5. 发明公开

EP4099372A1 CONDUCTIVE VIA STRUCTURES FOR GATE CONTACT OR TRENCH CONTACT 审中-实审
公开(公告)号：EP4099372A1
公开(公告)日：2022-12-07
申请号：EP22171616.0
申请日：2022-05-04
申请人： INTEL Corporation
发明人： GHANI, Tahir , WALLACE, Charles , GULER, Leonard
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L29/423
摘要： Conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures. A plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of a plurality of gate structures and co-planar with an uppermost surface of a plurality of conductive trench contact structures. A dielectric layer is over the plurality of gate structures, over the plurality of conductive trench contact structures, and over the plurality of dielectric spacers. The dielectric layer has a planar uppermost surface. An opening is in the dielectric layer, the opening exposing one of the plurality of gate structures or one of the plurality of conductive trench contact structures. A conductive via is in the opening. The conductive via has an uppermost surface co-planar with the planar uppermost surface of the dielectric layer.

6. 发明公开

EP4109510A1 EXTREME ULTRAVIOLET LITHOGRAPHY PATTERNING WITH ASSIST FEATURES 审中-实审
公开(公告)号：EP4109510A1
公开(公告)日：2022-12-28
申请号：EP22163744.0
申请日：2022-03-23
申请人： INTEL Corporation
发明人： GHANI, Tahir , WALLACE, Charles , ABDALLAH, Hossam , GULER, Leonard , FARIAS, Dario , CHANG, Tsuan-Chung , TSAI, Chia-Ho , SINGH, Chetana , TEWELDEBRHAN, Desalegne , JOACHIM, Robert , LIU, Shengsi
IPC分类号： H01L21/8234 , H01L29/66
摘要： Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.

7. 发明公开

EP4102552A1 NARROW CONDUCTIVE STRUCTURES FOR GATE CONTACT OR TRENCH CONTACT 审中-实审
公开(公告)号：EP4102552A1
公开(公告)日：2022-12-14
申请号：EP22169622.2
申请日：2022-04-25
申请人： INTEL Corporation
发明人： GULER, Leonard , HARAN, Mohit , GHANI, Tahir , WALLACE, Charles
IPC分类号： H01L21/768
摘要： Narrow conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric liner is along the plurality of dielectric spacers over the plurality of gate structures. A plurality of conductive pin structures is between the dielectric liner, individual ones of the plurality of conductive pin structures on corresponding ones of the plurality of gate structures.

8. 发明公开

EP4439675A2 TRANSISTOR WITH CHANNEL-SYMMETRIC GATE 审中-公开
公开(公告)号：EP4439675A2
公开(公告)日：2024-10-02
申请号：EP23214822.1
申请日：2023-12-07
申请人： INTEL Corporation
发明人： KOH, Shao-Ming , MORROW, Patrick , MEHTA, Nikhil , GULER, Leonard , NASKAR, Sudipto , DAVIS, Alison , LAVRIC, Dan , PRINCE, Matthew , LUCE, Jeanne , WALLACE, Charles , VOGELSBERG, Cortnie , PAI, Rajaram , KILROY, Caitlin , AMONOO, Jojo , PURSEL, Sean , GOTLIB, Yulia
IPC分类号： H01L29/423 , H01L29/775 , H01L29/06
CPC分类号： H01L29/775 , H01L29/0673 , H01L29/42376
摘要： Transistor structures comprising a gate electrode, or "gate," that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

9. 发明公开

EP4435841A1 CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION 审中-公开
公开(公告)号：EP4435841A1
公开(公告)日：2024-09-25
申请号：EP23209725.3
申请日：2023-11-14
申请人： INTEL Corporation
发明人： ALLEN, Gary , WALLACE, Charles , ENGEL, Clifford , GULER, Leonard , LIU, Shengsi , OBRIEN, Thomas , ZHU, Baofu , ACHARYA, Saurabh
IPC分类号： H01L21/768 , H01L23/485
CPC分类号： H01L23/485 , H01L21/76837 , H01L21/76895 , H01L21/7685
摘要： Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.

10. 发明公开

EP4016601A1 CONTACT OVER ACTIVE GATE STRUCTURES WITH TAPERED GATE OR TRENCH CONTACT FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION 审中-公开
公开(公告)号：EP4016601A1
公开(公告)日：2022-06-22
申请号：EP21198397.8
申请日：2021-09-22
申请人： INTEL Corporation
发明人： WALLACE, Charles , HARAN, Mohit , WEI, Andy Chih-Hung
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L21/8234
摘要： Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.

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